AMD Athlon Processor x86 Optimization Manual page 182

AMD Athlon™ Processor x86 Code Optimization
Table 11. Performance-Monitoring Counters (Continued)
Event Source
Number Unit
7Ah BU
80h PC
81h PC
82h PC
83h PC
84h PC
85h PC
86h PC
87h PC
88h PC
89h PC
C0h FR
C1h FR
C2h FR
C3h FR
C4h FR
C5h FR
C6h FR
C8h FR
C9h FR
CAh FR
CDh FR
CEh FR
CFh FR
D0h FR
D1h FR
D2h FR
D3h FR
D4h FR
166
Notes / Unit Mask (bits 15–8)
22007E/0—November 1999
Event Description
Cycles that at least one fill request
waited to use the L2
Instruction cache fetches
Instruction cache misses
Instruction cache refills from L2
Instruction cache refills from system
L1 ITLB misses (and L2 ITLB hits)
(L1 and) L2 ITLB misses
Snoop resyncs
Instruction fetch stall cycles
Return stack hits
Return stack overflow
Retired instructions (includes
exceptions, interrupts, resyncs)
Retired Ops
Retired branches (conditional,
unconditional, exceptions, interrupts)
Retired branches mispredicted
Retired taken branches
Retired taken branches mispredicted
Retired far control transfers
Retired near returns
Retired near returns mispredicted
Retired indirect branches with target
mispredicted
Interrupts masked cycles (IF=0)
Interrupts masked while pending cycles
(INTR while IF=0)
Number of taken hardware interrupts
Instruction decoder empty
Dispatch stalls (event masks D2h
through DAh below combined)
Branch abort to retire
Serialize
Segment load stall
Performance Counter Usage