Figure 17. Mtrrphysmaskn Register Format - AMD Athlon Processor x86 Optimization Manual

AMD Athlon™ Processor x86 Code Optimization
63
Reserved
Symbol Description
Physical Mask 24-Bit Mask
V Variable Range Register Pair Enabled 11
(V = 0 at reset)

Figure 17. MTRRphysMaskn Register Format

184
36
Bits
35–12
Note: A software attempt to write to reserved bits will generate a
general protection exception.
Physical Specifies a 24-bit mask to determine the range of
Mask the region defined in the register pair.
V Enables the register pair when set (V = 0 at reset).
Mask values can represent discontinuous ranges (when the
mask defines a lower significant bit as zero and a higher
significant bit as one). In a discontinuous range, the memory
area not mapped by the mask value is set to the default type.
Discontinuous ranges should not be used.
The range that is mapped by the variable-range MTRR register
pair must meet the following range size and alignment rule:
Each defined memory range must have a size equal to 2
< n < 36).
The base address for the address pair must be aligned to a
n
similar 2 boundary.
An example of a variable MTRR pair is as follows:
To map the address range from 8 Mbytes (0080_0000h) to
16 Mbytes (00FF_FFFFh) as writeback memory, the base
register should be loaded with 80_0006h, and the mask
should be loaded with FFF8_00800h.
35
Physical Mask
22007E/0—November 1999
12 11 10 0
V
n
(11
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