Floating-Point Execution Unit; Figure 3. Floating-Point Unit Block Diagram - AMD Athlon Processor x86 Optimization Manual

22007E/0—November 1999

Floating-Point Execution Unit

Instruction Control Unit
Instruction Control Unit

Figure 3. Floating-Point Unit Block Diagram

AMD Athlon™ Processor Microarchitecture
The floating-point execution unit (FPU) is implemented as a
coprocessor that has its own out-of-order control in addition to
the data path. The FPU handles all register operations for x87
instructions, all 3DNow! operations, and all MMX operations.
The FPU consists of a stack renaming unit, a register renaming
unit, a scheduler, a register file, and three parallel execution
units. Figure 3 shows a block diagram of the dataflow through
the FPU.
FPU Register File (88-entry)
FPU Register File (88-entry)
FADD
FADD
• MMX™ ALU
• MMX™ ALU
• 3DNow!™
• 3DNow!™
As shown in Figure 3 on page 137, the floating-point logic uses
three separate execution positions or pipes for superscalar x87,
3DNow! and MMX operations. The first of the three pipes is
generally known as the adder pipe (FADD), and it contains
3DNow! add, MMX ALU/shifter, and floating-point add
execution units. The second pipe is known as the multiplier
(FMUL). It contains a 3DNow!/MMX multiplier/reciprocal unit,
an MMX ALU and a floating-point multiplier/divider/square
root unit. The third pipe is known as the floating-point
load/store (FSTORE), which handles floating-point constant
loads (FLDZ, FLDPI, etc.), stores, FILDs, as well as many OP
primitives used in VectorPath sequences.
AMD Athlon™ Processor x86 Code Optimization
Stack Map
Stack Map
Register Rename
Register Rename
Scheduler (36-entry)
Scheduler (36-entry)
FMUL
FMUL
• MMX ALU
• MMX ALU
FSTORE
FSTORE
• MMX Mul
• MMX Mul
• 3DNow!
• 3DNow!
Pipeline Pipeline
Stage Stage
7 7
8 8
9 9
10
10
11
11
12 12
to to
15 15
137