Cache And Memory Optimizations; Memory Size And Alignment Issues; Avoid Memory Size Mismatches - AMD Athlon Processor x86 Optimization Manual

22007E/0—November 1999

Memory Size and Alignment Issues

Avoid Memory Size Mismatches

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Memory Size and Alignment Issues
Cache and Memory
Optimizations
This chapter describes code optimization techniques that take
advantage of the large L1 caches and high-bandwidth buses of
the AMD Athlon™ processor. Guidelines are listed in order of
importance.
Avoid memory size mismatches when instructions operate on
the same data. For instructions that store and reload the same
data, keep operands aligned and keep the loads/stores of each
operand the same size. The following code examples result in a
store-to-load-forwarding (STLF) stall:
Example 1 (Avoid):
MOV DWORD PTR [FOO], EAX
MOV DWORD PTR [FOO+4], EDX
FLD QWORD PTR [FOO]
Avoid large-to-small mismatches, as shown in the following
code:
Example 2 (Avoid):
FST QWORD PTR [FOO]
MOV EAX, DWORD PTR [FOO]
MOV EDX, DWORD PTR [FOO+4]
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