AMD Athlon Processor x86 Optimization Manual page 226

AMD Athlon™ Processor x86 Code Optimization
Table 20. MMX™ Instructions (Continued)
Instruction Mnemonic
PSRAW mmreg1, mmreg2
PSRAW mmreg, mem64
PSRAW mmreg, imm8
PSRAD mmreg1, mmreg2
PSRAD mmreg, mem64
PSRAD mmreg, imm8
PSRLD mmreg1, mmreg2
PSRLD mmreg, mem64
PSRLD mmreg, imm8
PSRLQ mmreg1, mmreg2
PSRLQ mmreg, mem64
PSRLQ mmreg, imm8
PSRLW mmreg1, mmreg2
PSRLW mmreg, mem64
PSRLW mmreg, imm8
PSUBB mmreg1, mmreg2
PSUBB mmreg, mem64
PSUBD mmreg1, mmreg2
PSUBD mmreg, mem64
PSUBSB mmreg1, mmreg2
PSUBSB mmreg, mem64
PSUBSW mmreg1, mmreg2
PSUBSW mmreg, mem64
PSUBUSB mmreg1, mmreg2
PSUBUSB mmreg, mem64
PSUBUSW mmreg1, mmreg2
PSUBUSW mmreg, mem64
PSUBW mmreg1, mmreg2
PSUBW mmreg, mem64
PUNPCKHBW mmreg1, mmreg2
PUNPCKHBW mmreg, mem64
Notes:
1. Bits 2, 1, and 0 of the modR/M byte select the integer register.
210
Prefix First ModR/M
Byte(s) Byte Byte
0Fh E1h 11-xxx-xxx
0Fh E1h mm-xxx-xxx DirectPath
0Fh 71h 11-100-xxx
0Fh E2h 11-xxx-xxx
0Fh E2h mm-xxx-xxx DirectPath
0Fh 72h 11-100-xxx
0Fh D2h 11-xxx-xxx
0Fh D2h mm-xxx-xxx DirectPath
0Fh 72h 11-010-xxx
0Fh D3h 11-xxx-xxx
0Fh D3h mm-xxx-xxx DirectPath
0Fh 73h 11-010-xxx
0Fh D1h 11-xxx-xxx
0Fh D1h mm-xxx-xxx DirectPath
0Fh 71h 11-010-xxx
0Fh F8h 11-xxx-xxx
0Fh F8h mm-xxx-xxx DirectPath
0Fh FAh 11-xxx-xxx
0Fh FAh mm-xxx-xxx DirectPath
0Fh E8h 11-xxx-xxx
0Fh E8h mm-xxx-xxx DirectPath
0Fh E9h 11-xxx-xxx
0Fh E9h mm-xxx-xxx DirectPath
0Fh D8h 11-xxx-xxx
0Fh D8h mm-xxx-xxx DirectPath
0Fh D9h 11-xxx-xxx
0Fh D9h mm-xxx-xxx DirectPath
0Fh F9h 11-xxx-xxx
0Fh F9h mm-xxx-xxx DirectPath
0Fh 68h 11-xxx-xxx
0Fh 68h mm-xxx-xxx DirectPath
22007E/0—November 1999
Decode
FPU Pipe(s)
Type
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
Instruction Dispatch and Execution Resources
Notes