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Athlon Processor x86
Optimization manual
AMD Athlon Processor x86 Optimization Manual page 11
X86 code optimization
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22007E/0-November 1999
List of Figures
Figure 1. AMD Athlon™ Processor Block Diagram
. . . . . . . . . . . 131
Figure 2. Integer Execution Pipeline
. . . . . . . . . . . . . . . . . . . . . . . 135
Figure 3. Floating-Point Unit Block Diagram
. . . . . . . . . . . . . . . . 137
Figure 4. Load/Store Unit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 5. Fetch/Scan/Align/Decode Pipeline Hardware
. . . . . . . . 142
Figure 6. Fetch/Scan/Align/Decode Pipeline Stages
. . . . . . . . . . . 142
Figure 7. Integer Execution Pipeline
. . . . . . . . . . . . . . . . . . . . . . . 144
Figure 8. Integer Pipeline Stages
. . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 9. Floating-Point Unit Block Diagram
. . . . . . . . . . . . . . . . 146
Figure 10. Floating-Point Pipeline Stages
. . . . . . . . . . . . . . . . . . . . 146
Figure 11. PerfEvtSel[3:0] Registers
. . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 12. MTRR Mapping of Physical Memory
. . . . . . . . . . . . . . . 173
Figure 13. MTRR Capability Register Format
. . . . . . . . . . . . . . . . 174
Figure 14. MTRR Default Type Register Format
. . . . . . . . . . . . . . 175
Figure 15. Page Attribute Table (MSR 277h)
. . . . . . . . . . . . . . . . . 177
Figure 16. MTRRphysBasen Register Format
. . . . . . . . . . . . . . . . . 183
Figure 17. MTRRphysMaskn Register Format
. . . . . . . . . . . . . . . . 184
List of Figures
AMD Athlon™ Processor x86 Code Optimization
xi
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