AMD Athlon Processor x86 Optimization Manual page 159

22007E/0—November 1999
Cycle 1–FETCH
Cycle 2–SCAN
Cycle 3 (DirectPath)–
ALIGN1
Cycle 3 (VectorPath)–
MECTL
Cycle 4 (DirectPath)–
ALIGN2
Cycle 4 (VectorPath)–
MEROM
Cycle 5 (DirectPath)–
EDEC
Cycle 5 (VectorPath)–
MEDEC/MESEQ
Cycle 6–
IDEC/Rename
Fetch and Decode Pipeline Stages
The FETCH pipeline stage calculates the address of the next
x86 instruction window to fetch from the processor caches or
system memory.
SCAN determines the start and end pointers of instructions.
SCAN can send up to six aligned instructions (DirectPath and
VectorPath) to ALIGN1 and only one VectorPath instruction to
the microcode engine (MENG) per cycle.
Because each 8-byte buffer (quadword queue) can contain up to
three instructions, ALIGN1 can buffer up to a maximum of nine
instructions, or 24 instruction bytes. ALIGN1 tries to send three
instructions from an 8-byte buffer to ALIGN2 per cycle.
For VectorPath instructions, the microcode engine control
(MECTL) stage of the pipeline generates the microcode entry
points.
ALIGN2 prioritizes prefix bytes, determines the opcode,
ModR/M, and SIB bytes for each instruction and sends the
accumulated prefix information to EDEC.
In the microcode engine ROM (MEROM) pipeline stage, the
entry-point generated in the previous cycle, MECTL, is used to
index into the MROM to obtain the microcode lines necessary
to decode the instruction sent by SCAN.
The early decode (EDEC) stage decodes information from the
DirectPath stage (ALIGN2) and VectorPath stage (MEROM)
into MacroOPs. In addition, EDEC determines register
pointers, flag updates, immediate values, displacements, and
other information. EDEC then selects either MacroOPs from
the DirectPath or MacroOPs from the VectorPath to send to the
instruction decoder (IDEC) stage.
The microcode engine decode (MEDEC) stage converts x86
instructions into MacroOPs. The microcode engine sequencer
(MESEQ) performs the sequence controls (redirects and
exceptions) for the MENG.
At the instruction decoder (IDEC)/rename stage, integer and
floating-point MacroOPs diverge in the pipeline. Integer
MacroOPs are scheduled for execution in the next cycle.
Floating-point MacroOPs have their floating-point stack
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