AMD Athlon Processor x86 Optimization Manual page 137

22007E/0—November 1999
$$xform:
ADD
MOVQ
MOVQ
ADD
MOVQ
MOVQ
PUNPCKLDQ MM0, MM0
MOVQ
PFMUL
PUNPCKHDQ MM2, MM2
PFMUL
MOVQ
MOVQ
MOVQ
PFMUL
MOVQ
PUNPCKLDQ MM1, MM1
PFMUL
MOVQ
PFMUL
PFADD
MOVQ
PFMUL
PFADD
MOVQ
PUNPCKHDQ MM6, MM6
PFADD
PFMUL
PFMUL
PFADD
PFADD
MOVQ
PFADD
MOVQ
DEC
JNZ
FEMMS
}
}
Optimized Matrix Multiplication
EBX, 16
MM0, QWORD PTR [EDX]
MM1, QWORD PTR [EDX+8]
EDX, 16
MM2, MM0
MM3, QWORD PTR [EAX+M00] ;m[0][1] | m[0][0]
MM4, QWORD PTR [EAX+M10] ;m[1][1] | m[1][0]
MM3, MM0
MM4, MM2
MM5, QWORD PTR [EAX+M02] ;m[0][3] | m[0][2]
MM7, QWORD PTR [EAX+M12] ;m[1][3] | m[1][2]
MM6, MM1
MM5, MM0
MM0, QWORD PTR [EAX+M20] ;m[2][1] | m[2][0]
MM7, MM2
MM2, QWORD PTR [EAX+M22] ;m[2][3] | m[2][2]
MM0, MM1
MM3, MM4
MM4, QWORD PTR [EAX+M30] ;m[3][1] | m[3][0]
MM2, MM1
MM5, MM7
MM1, QWORD PTR [EAX+M32] ;m[3][3] | m[3][2]
MM3, MM0
MM4, MM6
MM1, MM6
MM5, MM2
MM3, MM4
[EBX-16], MM3
MM5, MM1
[EBX-8], MM5
ECX
$$XFORM
AMD Athlon™ Processor x86 Code Optimization
;res++
;v->y | v->x
;v->w | v->z
;v++
;v->y | v->x
;v->x | v->x
;v->x*m[0][1] | v->x*m[0][0]
;v->y | v->y
;v->y*m[1][1] | v->y*m[1][0]
;v->w | v->z
;v->x*m[0][3] | v0>x*m[0][2]
;v->z | v->z
;v->y*m[1][3] | v->y*m[1][2]
;v->z*m[2][1] | v->z*m[2][0]
;v->x*m[0][1]+v->y*m[1][1] |
; v->x*m[0][0]+v->y*m[1][0]
;v->z*m[2][3] | v->z*m[2][2]
;v->x*m[0][3]+v->y*m[1][3] |
; v->x*m[0][2]+v->y*m[1][2]
;v->w | v->w
;v->x*m[0][1]+v->y*m[1][1]+v->z*m[2][1] |
; v->x*m[0][0]+v->y*m[1][0]+v->z*m[2][0]
;v->w*m[3][1] | v->w*m[3][0]
;v->w*m[3][3] | v->w*m[3][2]
;v->x*m[0][3]+v->y*m[1][3]+v->z*m[2][3] |
; v->x*m[0][2]+v->y*m[1][2]+v->z*m[2][2]
;v->x*m[0][1]+v->y*m[1][1]+v->z*m[2][1]+
; v->w*m[3][1] | v->x*m[0][0]+v->y*m[1][0]+
; v->z*m[2][0]+v->w*m[3][0]
;store res->y | res->x
;v->x*m[0][3]+v->y*m[1][3]+v->z*m[2][3]+
; v->w*m[3][3] | v->x*m[0][2]+v->y*m[1][2]+
; v->z*m[2][2]+v->w*m[3][2]
;store res->w | res->z
;numverts--
;until numverts == 0
;clear MMX state
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