Table 22. Floating-Point Instructions - AMD Athlon Processor x86 Optimization Manual

AMD Athlon™ Processor x86 Code Optimization
Table 21. MMX™ Extensions (Continued)
Instruction Mnemonic
PMINSW mmreg, mem64
PMINUB mmreg1, mmreg2
PMINUB mmreg, mem64
PMOVMSKB reg32, mmreg
PMULHUW mmreg1, mmreg2
PMULHUW mmreg, mem64
PSADBW mmreg1, mmreg2
PSADBW mmreg, mem64
PSHUFW mmreg1, mmreg2, imm8
PSHUFW mmreg, mem64, imm8
PREFETCHNTA mem8
PREFETCHT0 mem8
PREFETCHT1 mem8
PREFETCHT2 mem8
SFENCE
Notes:
1. For the PREFETCHNTA/T0/T1/T2 instructions, the mem8 value refers to an address in the 64-byte line that will be prefetched.

Table 22. Floating-Point Instructions

Instruction Mnemonic
F2XM1
FABS
FADD ST, ST(i)
FADD [mem32real]
FADD ST(i), ST
FADD [mem64real]
FADDP ST(i), ST
FBLD [mem80]
FBSTP [mem80]
FCHS
FCLEX
Notes:
1. The last three bits of the modR/M byte select the stack entry ST(i).
212
Prefix First ModR/M
Byte(s) Byte Byte
0Fh EAh mm-xxx-xxx DirectPath
0Fh DAh 11-xxx-xxx
0Fh DAh mm-xxx-xxx DirectPath
0Fh D7h
0Fh E4h 11-xxx-xxx
0Fh E4h mm-xxx-xxx DirectPath
0Fh F6h 11-xxx-xxx
0Fh F6h mm-xxx-xxx DirectPath
0Fh 70h
0Fh 70h
0Fh 18h
0Fh 18h
0Fh 18h
0Fh 18h
0Fh AEh
First Second ModR/M
Byte Byte Byte
D9h F0h
D9h E1h
D8h 11-000-xxx
D8h mm-000-xxx DirectPath
DCh 11-000-xxx
DCh mm-000-xxx DirectPath
DEh 11-000-xxx
DFh mm-100-xxx VectorPath
DFh mm-110-xxx VectorPath
D9h E0h
DBh E2h
Decode FPU
Type Pipe(s)
FADD/FMUL
DirectPath FADD/FMUL
FADD/FMUL
VectorPath
DirectPath FMUL
FMUL
DirectPath FADD
FADD
DirectPath FADD/FMUL
DirectPath FADD/FMUL
DirectPath -
DirectPath -
DirectPath -
DirectPath -
VectorPath -
Decode FPU
Type Pipe(s)
VectorPath
DirectPath FMUL
DirectPath FADD
FADD
DirectPath FADD
FADD
DirectPath FADD
DirectPath FMUL
VectorPath
Instruction Dispatch and Execution Resources
22007E/0—November 1999
Notes
1
1
1
1
Note
1
1
1