Page Attribute Table (Pat); Figure 15. Page Attribute Table (Msr 277H) - AMD Athlon Processor x86 Optimization Manual

22007E/0—November 1999

Page Attribute Table (PAT)

MSR Access
31
63
Reserved

Figure 15. Page Attribute Table (MSR 277h)

Page Attribute Table (PAT)
not affected by this issue, only the variable range (and MTRR
DefType) registers are affected.
The Page Attribute Table (PAT) is an extension of the page
table entry format, which allows the specification of memory
types to regions of physical memory based on the linear
address. The PAT provides the same functionality as MTRRs
with the flexibility of the page tables. It provides the operating
systems and applications to determine the desired memory
type for optimal performance. PAT support is detected in the
feature flags (bit 16) of the CPUID instruction.
The PAT is located in a 64-bit MSR at location 277h. It is
illustrated in Figure 15. Each of the eight PAn fields can contain
the memory type encodings as described in Table 12 on
page 174. An attempt to write an undefined memory type
encoding into the PAT will generate a GP fault.
26 24 18
PA3
58 56 50
PA7
AMD Athlon™ Processor x86 Code Optimization
16 10
PA1
PA2
48 42
PA5
PA6
2 0
8
PA0
34 32
40
PA4
177