Table of Contents
Advertisement
AMD Athlon™ Processor x86 Code Optimization
Floating-Point Pipeline Stages
Instruction Control Unit
Instruction Control Unit
Figure 9. Floating-Point Unit Block Diagram
7
8
STKREN
REGREN
Figure 10. Floating-Point Pipeline Stages
146
The floating-point unit (FPU) is implemented as a coprocessor
that has its own out-of-order control in addition to the data
path. The FPU handles all register operations for x87
instructions, all 3DNow! operations, and all MMX operations.
The FPU consists of a stack renaming unit, a register renaming
unit, a scheduler, a register file, and three parallel execution
units. Figure 9 shows a block diagram of the dataflow through
the FPU.
FPU Register File (88-entry)
FPU Register File (88-entry)
FADD
FADD
• MMX™ ALU
• MMX™ ALU
• 3DNow!™
• 3DNow!™
The floating-point pipeline stages 7–15 are shown in Figure 10
and described in the following sections. Note that the
floating-point pipe and integer pipe separates at cycle 7.
9
10
SCHEDW
SCHED
Stack Map
Stack Map
Register Rename
Register Rename
Scheduler (36-entry)
Scheduler (36-entry)
FMUL
FMUL
• MMX ALU
• MMX ALU
FSTORE
FSTORE
• MMX Mul
• MMX Mul
• 3DNow!
• 3DNow!
11
12
FREG
FEXE1
22007E/0—November 1999
Pipeline
Pipeline
Stage
Stage
7
7
8
8
9
9
10
10
11
11
12
12
to
to
15
15
15
FEXE4
Floating-Point Pipeline Stages
Advertisement
Table of Contents
