AMD Athlon Processor x86 Optimization Manual page 223

22007E/0—November 1999
Table 19. Integer Instructions (Continued)
Instruction Mnemonic
XADD mreg8, reg8
XADD mem8, reg8
XADD mreg16/32, reg16/32
XADD mem16/32, reg16/32
XCHG reg8, mreg8
XCHG reg8, mem8
XCHG reg16/32, mreg16/32
XCHG reg16/32, mem16/32
XCHG EAX, EAX
XCHG EAX, ECX
XCHG EAX, EDX
XCHG EAX, EBX
XCHG EAX, ESP
XCHG EAX, EBP
XCHG EAX, ESI
XCHG EAX, EDI
XLAT
XOR mreg8, reg8
XOR mem8, reg8
XOR mreg16/32, reg16/32
XOR mem16/32, reg16/32
XOR reg8, mreg8
XOR reg8, mem8
XOR reg16/32, mreg16/32
XOR reg16/32, mem16/32
XOR AL, imm8
XOR EAX, imm16/32
XOR mreg8, imm8
XOR mem8, imm8
XOR mreg16/32, imm16/32
XOR mem16/32, imm16/32
XOR mreg16/32, imm8 (sign extended)
XOR mem16/32, imm8 (sign extended)
Instruction Dispatch and Execution Resources
AMD Athlon™ Processor x86 Code Optimization
First Second ModR/M
Byte Byte Byte
0Fh C0h 11-100-xxx
0Fh C0h mm-100-xxx VectorPath
0Fh C1h 11-101-xxx
0Fh C1h mm-101-xxx VectorPath
86h 11-xxx-xxx
86h mm-xxx-xxx VectorPath
87h 11-xxx-xxx
87h mm-xxx-xxx VectorPath
90h
91h
92h
93h
94h
95h
96h
97h
D7h
30h 11-xxx-xxx
30h mm-xxx-xxx DirectPath
31h 11-xxx-xxx
31h mm-xxx-xxx DirectPath
32h 11-xxx-xxx
32h mm-xxx-xxx DirectPath
33h 11-xxx-xxx
33h mm-xxx-xxx DirectPath
34h
35h
80h 11-110-xxx
80h mm-110-xxx DirectPath
81h 11-110-xxx
81h mm-110-xxx DirectPath
83h 11-110-xxx
83h mm-110-xxx DirectPath
Decode
Type
VectorPath
VectorPath
VectorPath
VectorPath
DirectPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
VectorPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
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