Table 11. Performance-Monitoring Counters - AMD Athlon Processor x86 Optimization Manual

AMD Athlon™ Processor x86 Code Optimization

Table 11. Performance-Monitoring Counters

Event Source
Number Unit
1xxx_xxxxb = reserved
x1xx_xxxxb = HS
xx1x_xxxxb = GS
xxx1_xxxxb = FS
20h LS
xxxx_1xxxb = DS
xxxx_x1xxb = SS
xxxx_xx1xb = CS
xxxx_xxx1b = ES
21h LS
40h DC
41h DC
xxx1_xxxxb = Modified (M)
xxxx_1xxxb = Owner (O)
42h DC
xxxx_x1xxb = Exclusive (E)
xxxx_xx1xb = Shared (S)
xxxx_xxx1b = Invalid (I)
xxx1_xxxxb = Modified (M)
xxxx_1xxxb = Owner (O)
43h DC
xxxx_x1xxb = Exclusive (E)
xxxx_xx1xb = Shared (S)
xxxx_xxx1b = Invalid (I)
xxx1_xxxxb = Modified (M)
xxxx_1xxxb = Owner (O)
44h DC
xxxx_x1xxb = Exclusive (E)
xxxx_xx1xb = Shared (S)
xxxx_xxx1b = Invalid (I)
45h DC
46h DC
47h DC
64h BU
164
greater than or equal to the counter mask. Otherwise if this
field is zero, then the counter increments by the total number of
events.
Notes / Unit Mask (bits 15–8)
22007E/0—November 1999
Event Description
Segment register loads
Stores to active instruction stream
Data cache accesses
Data cache misses
Data cache refills
Data cache refills from system
Data cache writebacks
L1 DTLB misses and L2 DTLB hits
L1 and L2 DTLB misses
Misaligned data references
DRAM system requests
Performance Counter Usage