AMD Athlon Processor x86 Optimization Manual page 232

AMD Athlon™ Processor x86 Code Optimization
Table 22. Floating-Point Instructions (Continued)
Instruction Mnemonic
FSTCW [mem16]
FSTENV [mem14byte]
FSTENV [mem28byte]
FSTP [mem32real]
FSTP [mem64real]
FSTP [mem80real]
FSTP ST(i)
FSTSW AX
FSTSW [mem16]
FSUB [mem32real]
FSUB [mem64real]
FSUB ST, ST(i)
FSUB ST(i), ST
FSUBP ST, ST(i)
FSUBR [mem32real]
FSUBR [mem64real]
FSUBR ST, ST(i)
FSUBR ST(i), ST
FSUBRP ST(i), ST
FTST
FUCOM
FUCOMI ST, ST(i)
FUCOMIP ST, ST(i)
FUCOMP
FUCOMPP
FWAIT
FXAM
FXCH
FXTRACT
FYL2X
FYL2XP1
Notes:
1. The last three bits of the modR/M byte select the stack entry ST(i).
216
First Second ModR/M
Byte Byte Byte
D9h mm-111-xxx VectorPath
D9h mm-110-xxx VectorPath
D9h mm-110-xxx VectorPath
D9h mm-011-xxx DirectPath
DDh mm-011-xxx DirectPath
D9h mm-111-xxx VectorPath
DDh 11-011-xxx
DFh E0h
DDh mm-111-xxx VectorPath
D8h mm-100-xxx DirectPath
DCh mm-100-xxx DirectPath
D8h 11-100-xxx
DCh 11-101-xxx
DEh 11-101-xxx
D8h mm-101-xxx DirectPath
DCh mm-101-xxx DirectPath
D8h 11-100-xxx
DCh 11-101-xxx
DEh 11-100-xxx
D9h E4h
DDh 11-100-xxx
DB E8-EFh
DF E8-EFh
DDh 11-101-xxx
DAh E9h
9Bh
D9h E5h
D9h 11-001-xxx
D9h F4h
D9h F1h
D9h F9h
Decode FPU
Type Pipe(s)
FADD/FMUL
FADD/FMUL
DirectPath FADD/FMUL
VectorPath
FSTORE
FADD
FADD
DirectPath FADD
DirectPath FADD
DirectPath FADD
FADD
FADD
DirectPath FADD
DirectPath FADD
DirectPath FADD
DirectPath FADD
DirectPath FADD
VectorPath FADD
VectorPath FADD
DirectPath FADD
DirectPath FADD
DirectPath
VectorPath
DirectPath FADD/FMUL/FSTORE
VectorPath
VectorPath
VectorPath
Instruction Dispatch and Execution Resources
22007E/0—November 1999
Note
1
1
1
1
1
1