Figure 14. Mtrr Default Type Register Format - AMD Athlon Processor x86 Optimization Manual

22007E/0—November 1999
63
Reserved
Symbol Description
E MTRRs Enabled
FE Fixed Range Enabled
Type Default Memory Type

Figure 14. MTRR Default Type Register Format

Memory Type Range Register (MTRR) Mechanism
MTRR Default Type Register Format. The MTRR default type register
is defined as follows.
Bits
11
10
7–0
E MTRRs are enabled when set. All MTRRs (both fixed and
variable range) are disabled when clear, and all of
physical memory is mapped as uncacheable memory
(reset state = 0).
FE Fixed-range MTRRs are enabled when set. All MTRRs
are disabled when clear. When the fixed-range MTRRs
are enabled and an overlap occurs with a variable-range
MTRR, the fixed-range MTRR takes priority (reset state
= 0).
Type Defines the default memory type (reset state = 0). See
Table 13 for more details.
AMD Athlon™ Processor x86 Code Optimization
11 10 9 8
7 3
F
E
E
2 1 0
Type
175