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AMD Athlon™ Processor x86 Code Optimization
AMD Athlon™ Processor Microarchitecture Summary
4
The AMD Athlon processor brings superscalar performance
a nd hi gh op era t ing f req ue ncy t o P C s y st e m s r un ning
industry-standard x86 software. A brief summary of the
n ex t -g e n e ra t i o n d e s i g n f e a t u re s i m p l e m e n t e d i n t h e
AMD Athlon processor is as follows:
High-speed double-rate local bus interface
Large, split 128-Kbyte level-one (L1) cache
Dedicated backside level-two (L2) cache
Instruction predecode and branch detection during cache
line fills
Decoupled decode/execution core
Three-way x86 instruction decoding
Dynamic scheduling and speculative execution
Three-way integer execution
Three-way address generation
Three-way floating-point execution
3DNow!™
technology
multiple-data (SIMD) instruction extensions
Super data forwarding
Deep out-of-order integer and floating-point execution
Register renaming
Dynamic branch prediction
Th e A M D A t h l o n p ro c e s s o r c o m mu n i c a t e s t h ro u g h a
next-generation high-speed local bus that is beyond the current
Socket 7 or Super7™ bus standard. The local bus can transfer
data at twice the rate of the bus operating frequency by using
b o t h t h e r i s i n g a n d f a l l i n g e d g e s o f t h e c l o c k ( s e e
"A M D A t h l o n ™ S y s t e m B u s " o n p a g e 1 3 9 f o r m o re
information).
To reduce on-chip cache miss penalties and to avoid subsequent
data load or instruction fetch stalls, the AMD Athlon processor
has a dedicated high-speed backside L2 cache. The large
128-Kbyte L1 on-chip cache and the backside L2 cache allow the
and
MMX™
AMD Athlon™ Processor Microarchitecture Summary
22007E/0—November 1999
single-instruction
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