AMD Athlon Processor x86 Optimization Manual page 163

22007E/0—November 1999
Cycle 7–STKREN
Cycle 8–REGREN
Cycle 9–SCHEDW
Cycle 10–SCHED
Cycle 11–FREG
Cycle 12–15–
Floating-Point
Execution (FEXEC1–4)
Floating-Point Pipeline Stages
The stack rename (STKREN) pipeline stage in cycle 7 receives
up to three MacroOPs from IDEC and maps stack-relative
register tags to virtual register tags.
The register renaming (REGREN) pipeline stage in cycle 8 is
responsible for register renaming. In this stage, virtual register
tags are mapped into physical register tags. Likewise, each
destination is assigned a new physical register. The MacroOPs
are then sent to the 36-entry FPU scheduler.
The scheduler write (SCHEDW) pipeline stage in cycle 9 can
receive up to three MacroOPs per cycle.
The schedule (SCHED) pipeline stage in cycle 10 schedules up
to three MacroOPs per cycle from the 36-entry FPU scheduler
to the FREG pipeline stage to read register operands.
MacroOPs are sent when their operands and/or tags are
obtained.
The register file read (FREG) pipeline stage reads the
floating-point register file for any register source operands of
MacroOPs. The register file read is done before the MacroOPs
are sent to the floating-point execution pipelines.
The FPU has three logical pipes—FADD, FMUL, and FSTORE.
Each pipe may have several associated execution units. MMX
execution is in both the FADD and FMUL pipes, with the
exception of MMX instructions involving multiplies, which are
limited to the FMUL pipe. The FMUL pipe has special support
for long latency operations.
DirectPath/VectorPath operations are dispatched to the FPU
during cycle 6, but are not acted upon until they receive
validation from the ICU in cycle 7.
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