Table 19. Integer Instructions - AMD Athlon Processor x86 Optimization Manual

AMD Athlon™ Processor x86 Code Optimization

Table 19. Integer Instructions

Instruction Mnemonic
AAA
AAD
AAM
AAS
188
disp16/32—16-bit or 32-bit displacement value
disp32/48—32-bit or 48-bit displacement value
eXX—register width depending on the operand size
mem32real—32-bit floating-point value in memory
mem64real—64-bit floating-point value in memory
mem80real—80-bit floating-point value in memory
mmreg—MMX/3DNow! register
mmreg1—MMX/3DNow! register defined by bits 5, 4, and 3
of the modR/M byte
mmreg2—MMX/3DNow! register defined by bits 2, 1, and 0
of the modR/M byte
The second and third columns list all applicable encoding
opcode bytes.
The fourth column lists the modR/M byte used by the
instruction. The modR/M byte defines the instruction as
register or memory form. If mod bits 7 and 6 are documented as
mm (memory form), mm can only be 10b, 01b, or 00b.
The fifth column lists the type of instruction decode —
DirectPath or VectorPath (see "DirectPath Decoder" on page
13 3 and "Vec t orPa th D ec od e r" on pag e 13 3 fo r m o re
information). The AMD Athlon™ processor enhanced decode
logic can process three instructions per clock.
The FPU, MMX, and 3DNow! instruction tables have an
additional column that lists the possible FPU execution
pipelines available for use by any particular DirectPath
decoded operation. Typically, VectorPath instructions require
more than one execution pipe resource.
First
Byte
37h
D5h
D4h
3Fh
Second ModR/M Decode
Byte Byte
VectorPath
0Ah VectorPath
0Ah VectorPath
VectorPath
Instruction Dispatch and Execution Resources
22007E/0—November 1999
Type