AMD Athlon Processor x86 Optimization Manual page 213

22007E/0—November 1999
Table 19. Integer Instructions (Continued)
Instruction Mnemonic
LOOPE/LOOPZ disp8
LOOPNE/LOOPNZ disp8
LSL reg16/32, mreg16/32
LSL reg16/32, mem16/32
LSS reg16/32, mem32/48
LTR mreg16
LTR mem16
MOV mreg8, reg8
MOV mem8, reg8
MOV mreg16/32, reg16/32
MOV mem16/32, reg16/32
MOV reg8, mreg8
MOV reg8, mem8
MOV reg16/32, mreg16/32
MOV reg16/32, mem16/32
MOV mreg16, segment reg
MOV mem16, segment reg
MOV segment reg, mreg16
MOV segment reg, mem16
MOV AL, mem8
MOV EAX, mem16/32
MOV mem8, AL
MOV mem16/32, EAX
MOV AL, imm8
MOV CL, imm8
MOV DL, imm8
MOV BL, imm8
MOV AH, imm8
MOV CH, imm8
MOV DH, imm8
MOV BH, imm8
MOV EAX, imm16/32
MOV ECX, imm16/32
Instruction Dispatch and Execution Resources
AMD Athlon™ Processor x86 Code Optimization
First Second ModR/M
Byte Byte Byte
E1h
E0h
0Fh 03h 11-xxx-xxx
0Fh 03h mm-xxx-xxx VectorPath
0Fh B2h mm-xxx-xxx VectorPath
0Fh 00h 11-011-xxx
0Fh 00h mm-011-xxx VectorPath
88h 11-xxx-xxx
88h mm-xxx-xxx DirectPath
89h 11-xxx-xxx
89h mm-xxx-xxx DirectPath
8Ah 11-xxx-xxx
8Ah mm-xxx-xxx DirectPath
8Bh 11-xxx-xxx
8Bh mm-xxx-xxx DirectPath
8Ch 11-xxx-xxx
8Ch mm-xxx-xxx VectorPath
8Eh 11-xxx-xxx
8Eh mm-xxx-xxx VectorPath
A0h
A1h
A2h
A3h
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
Decode
Type
VectorPath
VectorPath
VectorPath
VectorPath
DirectPath
DirectPath
DirectPath
DirectPath
VectorPath
VectorPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
DirectPath
197