Keithley 2302 Instruction Manual page 159

Figure 8-1
Status model structure
Calibration Summary
(Always Zero)
Operation Complete
Query Error
Device Specific Error
Execution Error
Command Error
User Request
Power On
(Always Zero)
Measurement Event Registers
Condition
Register
Reading Overflow Channel 1 ROF1
Pulse Trigger Timeout Channel 1 PTT1
Reading Available Channel 1
RAV1
Reading Overflow Channel 2
ROF2
Pulse Trigger Timeout Channel 2 PTT2
RAV2
Reading Available Channel 2
Buffer Full Channel 1
BF1
BF2
Buffer Full Channel 2
11
12
13
14
(Always Zero) 15
:CONDition?
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Questionable Event Registers
Condition Event
Register Register
0 0 &
1 1
&
2 2 &
3 3
&
4 &
4
5 5 &
6 6
&
7
7 &
Cal &
Cal
9 9 &
10 10
&
&
11 11
&
12 12
13 13 &
14 14 &
15 15 &
:CONDition? [:EVENt]? :ENABle <NRf>
Output Queue
Standard Event Registers
Event
Event Enable
Register Register
OPC & OPC
1 1
&
&
QYE QYE
DDE & DDE
&
EXE EXE
&
CME CME
URQ & URQ
&
PON PON
8 & 8
9 & 9
10
10
&
&
11 11
&
12 12
13 & 13
14 & 14
15 & 15
*ESR? *ESE <NRf>
*ESE?
Event
Event Enable
Register
Register
0 &
0 0
1 1
& 1
2 2
& 2
ROF1 ROF1
&
PTT1 & PTT1
RAV1 & RAV1
ROF2 ROF2
&
PTT2 PTT2
&
RAV2 RAV2
&
BF1 BF1
&
BF2 BF2
&
11 & 11
&
12 12
13
& 13
14 14
&
15 & 15
[:EVENt]? :ENABle <NRf>
:ENABle?
Event
Enable
Register
0
1
2
3
4
5
6
Logical
7
OR
Cal
9
10
11
12
13
14
15
:ENABle?
Logical
OR
MSB = Measurement Summary Bit
EAV = Error Available
QSB = Questionable Summary Bit
MAV = Message Available
ESB = Event Summary Bit
RQS/MSS = Request for Service/Master Summary Staus
OSB = Operation Summary Bit
Condition
Register
VPT Channel 1
VPT1
VPT Channel 2 VPT2
Current Limit 1
CL1
Current Limit Tripped 1
CLT1
Heat Sink Shutdown
HSS
Power Supply Shutdown
PSS
Logical
Current Limit 2
CL2
OR
Current Limit Tripped 2 CLT2
10
11
12
13
14
(Always Zero)
15
:CONDition?
Status Structure 8-3
Error Queue
Service
Status Request
Byte
Enable
Register Register
MSB & MSB
1 & 1
EAV EAV
&
QSB
QSB
&
& MAV
MAV
ESB ESB
&
RQS/MSS 6
OSB OSB
&
*STB?
*SRE
*SRE?
Master Summary Status (MSS)
Note : RQS bit is in serial poll byte,
MSS bit is in *STB? response.
Operation Event Registers
Event
Event Enable
Register Register
0
0 0
&
VPT1
VPT1
&
VPT2
VPT2
&
CL1
CL1 &
CLT1 CLT1
&
HSS
& HSS
PSS PSS
&
CL2 & CL2
CLT2 & CLT2
9
9 & 9
10 & 10
&
11 11
&
12 12
13 13
&
14 & 14
&
15 15
[:EVENt]? :ENABle <NRf>
:ENABle?
Logical
OR
Logical
OR