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location 0x10800000 is the global base address for C64x+ Megamodule Core 0's L2 memory. C64x+
Megamodule Core 0 can access this location by either using 0x10800000 or 0x00800000. Any other
master on the device must use 0x10800000 only. Conversely, 0x00800000 can by used by any of the
three cores as their own L2 base addresses. For C64x+ Megamodule Core 0, as mentioned this is
equivalent to 0x10800000, for C64x+ Megamodule Core 1 this is equivalent to 0x11800000, and for
C64x+ Megamodule Core 2 this is equivalent to 0x12800000. Local addresses should only be used for
shared code or data, allowing a single image to be included in memory. Any code/data targeted to a
specific core, or a memory region allocated during run-time by a particular core should always use the
global address only.
5.3
Memory Protection
Memory protection allows an operating system to define who or what is authorized to access L1D, L1P,
and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16
pages of L1P (2KB each), 16 pages of L1D (2KB each), and up to 64 pages of L2. The L1D, L1P, and L2
memory controllers in the C64x+ Megamodule are equipped with a set of registers that specify the
permissions for each memory page. For L2, the number of protection pages and their sizes depend on the
L2 configuration of the device, as defined in the previous section. The actual sizes are listed in
ADDRESS RANGE
0x0080 0000 - 0x0087 FFFF
0x0088 0000 - 0x008F FFFF
0x0090 0000 - 0x0097 FFFF
0x0098 0000 - 0x009F FFFF
Table 5-2
shows the memory addresses used to access the L2 memory. Cells in normal font should be
used by the software for memory accesses. The L2 addresses are common between all three cores,
allowing for the same code to be run unmodified on each. Cells in italic (N/A) are not accessible. Memory
protection pages are 1/32nd of the size of each UMAP. The memory protection sizes are constant across
all three cores.
ADDRESS RANGE
0x0080 0000 - 0x0087 FFFF
0x0088 0000 - 0x008F FFFF
0x0090 0000 - 0x0097 FFFF
0x0098 0000 - 0x009F FFFF
Each page may be assigned with fully orthogonal user and supervisor read, write, and execute
permissions. Additionally, a page may be marked as either (or both) locally or globally accessible. A local
access is one initiated by the CPU, while a global access is initiated by a DMA (either IDMA or DMA
access by any C64x+ Megamodule or master peripheral).
The CPU and each of the system masters on the device are all assigned a privilege ID (see
The AIDx (x=0,1,2,3,4,5) and LOCAL bits of the memory protection page attribute registers specify the
memory page protection scheme as listed in
Whenever the CPU is the initiator of a memory transaction, the privilege mode (user or supervisor) in
which the CPU is running at that time is carried with those transactions. This includes EDMA3 transfers
that are programmed by the CPU. Other system masters (EMAC, RapidIO) are always in user mode.
Copyright © 2008–2010, Texas Instruments Incorporated
Table 5-1. L2 Memory Protection Page Sizes
C64x+ MEGAMODULE
CORE 0
32 KB
32 KB
N/A
N/A
Table 5-2. L2 Memory Address Ranges
C64x+ MEGAMODULE
CORE 0
UMAP 0
UMAP 0
N/A
N/A
Table
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SPRS552F – OCTOBER 2008 – REVISED JULY 2010
C64x+ MEGAMODULE
CORE 1
32 KB
32 KB
N/A
N/A
C64x+ MEGAMODULE
CORE 1
UMAP 0
UMAP 0
N/A
N/A
5-4.
:TMS320C6474
TMS320C6474
Table
5-1.
C64x+ MEGAMODULE
CORE 2
32 KB
32 KB
N/A
N/A
C64x+ MEGAMODULE
CORE 2
UMAP 0
UMAP 0
N/A
N/A
Table
5-3).
C64x+ Megamodule
61
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