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7.23 Frame Synchronization
Frame synchronization handles timing and time alignment on the device by coordinating timing between
the DSP cores. Up to 30 programmable events based on RP3 or system timer. One output is used for
exporting frame alignment to aid in synchronizing external components.
Frame synchronization assists with synchronization of clock inputs:
•
OBSAI RP1 compliant input for frame burst data.
•
UMTS frame synchronization boundary used as an alternative to RP1 for frame burst data.
•
System timer synchronization used as an alternative to RP1.
The user may select between the OBSAI RP1-compliant FSYNCCLK(P|N) and FRAMEBURST(P|N)
signals or the alternate, single-ended ALTFSYNCCLK and ALTFSYNCPULSE inputs to drive the timers.
C64x+
MODULE EVENTS
MEGAMODULE
CORE 0
FSEVT0
X
FSEVT1
X
FSEVT2
X
FSEVT3
X
FSEVT4
X
FSEVT5
X
FSEVT6
X
FSEVT7
X
FSEVT8
X
FSEVT9
X
FSEVT10
X
FSEVT11
X
FSEVT12
X
FSEVT13
X
FSEVT14
X
FSEVT15
X
FSEVT16
X
FSEVT17
X
FSEVT18
FSEVT19
FSEVT20
FSEVT21
FSEVT22
FSEVT23
FSEVT24
FSEVT25
FSEVT26
FSEVT27
FSEVT28
FSEVT29
FS_ERR_Alarm0
FS_ERR_Alarm1
FS_AIFFrameSync
Copyright © 2008–2010, Texas Instruments Incorporated
Table 7-90. FSYNC Event Connections
C64x+
C64x+
MEGAMODULE
MEGAMODULE
CORE 1
CORE 2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Submit Documentation Feedback
Product Folder Link(s)
:TMS320C6474
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
CIC0
CIC1
CIC2
TPCC
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Peripheral Information and Electrical Specifications
TMS320C6474
CIC3
TIMER
AIF
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
203
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