Texas Instruments TMS320C6474 Manual page 121

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7.8.3.2 PLL Multiplier Control Register
The PLL multiplier control register (PLLM) is shown in
register defines the input reference clock frequency multiplier.
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-12. PLL Multiplier Control Register (PLLM) [Hex Address: 029A 0110]
Table 7-26. PLL Multiplier Control Register (PLLM) Field Descriptions
Bit Field
31:5 Reserved
4:0 PLLM
(1) For more information, see
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Reserved
R-0
Value Description
0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
PLL multiplier bits. Defines the input reference clock frequency multiplier.
0h Bypass
3h x4 multiplier rate
4h x5 multiplier rate
. .
. .
. .
1Eh x31 multiplier rate
1Fh x32 multiplier rate
Section 7.8.4.
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SPRS552F – OCTOBER 2008 – REVISED JULY 2010
Figure 7-12 and described in
Reserved
R-0
5
Peripheral Information and Electrical Specifications
:TMS320C6474
TMS320C6474
Table 7-26. The PLLM
4
PLLM
R/W-0h
(1)
16
0
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