TMS320C6474
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
Table 7-49. Timing Requirements for McBSP as SPI Master: CLKSTP = 11b, CLKXP = 0
(see
Figure
7-31)
NO.
4
t
Setup time, DR valid before CLKX high
su(DRV-CKXH)
5
t
Hold time, DR valid after CLKX high
h(CKXH-DRV)
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
Table 7-50. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
(see
Figure
7-31)
NO.
1
t
Hold time, FSX low after CLKX low
h(CKXL-FXL)
2
t
Delay time, FSX low to CLKX high
d(FXL-CKXH)
3
t
Delay time, CLKX low to DX valid
d(CKXL-DXV)
Disable time, DX high impedance following
6
t
dis(CKXL-DXHZ)
last data bit from CLKX low
7
t
Delay time, FSX low to DX valid
d(FXL-DXV)
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) S = Sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
(3) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
(4) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master
clock (CLKX).
CLKX
1
FSX
6
DX
Bit 0
DR
Bit 0
Figure 7-31. McBSP Timing as SPI Master: CLKSTP = 11b, CLKXP = 0
146
Peripheral Information and Electrical Specifications
Master: CLKSTP = 11b, CLKXP = 0
PARAMETER
(3)
(4)
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Product Folder Link(s)
MASTER
MIN
MAX
12
4
(1)
(2)
MASTER
MIN
MAX
L - 2
L + 3
T - 2
T + 3
-2
-2
H - 2
H + 4
2
7
3
Bit(n-1)
(n-2)
4
5
Bit(n-1)
(n-2)
Copyright © 2008–2010, Texas Instruments Incorporated
:TMS320C6474
(1)
SLAVE
MIN
MAX
2 - 18P
5 + 36P
SLAVE
MIN
MAX
4
18P + 2.8
30P + 17
4
18P + 3
30P + 17
12P + 2
24P + 17
(n-3)
(n-4)
(n-3)
(n-4)
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UNIT
ns
ns
UNIT
ns
ns
ns
ns
ns
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