Texas Instruments TMS320C6474 Manual page 16

TMS320C6474
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
MODE NAME
No Boot
I2C Master Boot A
I2C Master Boot B
I2C Slave Boot
EMAC Master Boot
EMAC Slave Boot
EMAC Forced-Mode Boot
Reserved
Serial RapidIO Boot (Config 0)
Serial RapidIO Boot (Config 1)
Serial RapidIO Boot (Config 2)
Serial RapidIO Boot (Config 3)
C64x+ Megamodule Core 0 configures Serial RapidIO and EDMA, if required, and brings the code image
into the internal on-chip memory via the protocol defined by the boot method (SRIO bootloader) and then
C64x+ Megamodule Core 0 brings the other C64x+ Megamodule Cores out of reset. Note that SRIO boot
modes are only supported on port 0.
SRIO BOOT MODE
Bootmode 8 - Config 0
Bootmode 9 - Config 1
Bootmode 10 - Config 2
Bootmode 11 - Config 3
All the other BOOTMODE[3:0] modes are reserved.
2.4.2 Second-Level Bootloaders
Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader
allows for any level of customization to current boot methods as well as the definition of a completely
customized boot.
16 Device Overview
Table 2-3. C6474 Supported Boot Modes
BOOTMODE[3:0]
0000b No Boot (BOOTMODE[3:0] = 0000b)
0001b Slave I2C address is 0x50. C64x+ Megamodule Core 0 configures I2C, acts as a
master to the I2C bus and copies data from an I2C EEPROM or a device acting as an
I2C slave to the DSP using a predefined boot table format. The destination address
and length are contained within the boot table. After boot table copy is complete, the
C64x+ Megamodule Core 0 brings the other C64x+ Megamodule Cores out of reset
by setting to 1 the EVTPULSE4 bit (bit 4) of the C64x+ Megamodule Core EVTASRT
register.
0010b Similar to I2C boot A except the slave I2C address is 0x51.
0011 The C64x+ Megamodule Core 0 configures I2C and acts as a slave and will accept
data and code section packets through the I2C interface. It is required that an I2C
master in present in the system.
0100b TI Ethernet Boot, C64x+ Megamodule Core 0 configures EMAC0 and EDMA, if
required, and brings the code image into the internal on-chip memory via the protocol
0101b
defined by the boot method (EMAC bootloader). After initializing the on-chip memory
0110b
to the known state, C64x+ Megamodule Core 0 brings the other C64x+ Megamodule
Cores out of reset.
0111b Reserved
1000b The C64x+ Megamodule Core 0 configures the SRIO and an external host loads the
application via SRIO peripheral, using directIO protocol. A doorbell interrupt is used to
1001b
indicate that the code has been loaded. For more details on the Serial RapidIO
1010b
configurations, see
1011b
Table 2-4. Serial RapidIO (SRIO) Supported Boot Modes
SERDES CLOCK
125 MHz
125 MHz
156.25 MHz
156.25 MHz
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DESCRIPTION
Table 2-4.
LINK RATE
1.25 Gbps
3.125 Gbps
1.25 Gbps
3.125 Gbps
Copyright © 2008–2010, Texas Instruments Incorporated
:TMS320C6474
www.ti.com
BOOTMODE[3:0]
1000b
1001b
1010b
1011b