Device Overview; Device Characteristics - Texas Instruments TMS320C6474 Manual

Multicore digital signal processor
Hide thumbs Also See for TMS320C6474:
Table of Contents

Advertisement

TMS320C6474
SPRS552F – OCTOBER 2008 – REVISED JULY 2010

2 Device Overview

2.1

Device Characteristics

Table 2-1
provides an overview of the C6474 DSP. The tables show significant features of the C6474
device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type
with pin count.
HARDWARE FEATURES
Peripherals
DDR2 Memory Controller (32-bit bus width) [1.8 V I/O]
Not all peripherals pins
(clock memory = DDRREFCLK(N|P)
are available at the same
EDMA3 (64 independent channels [CPU/3 clock rate]
time.
High-speed 1x Serial RapidIO Port (2 lanes)
(For more detail, see
Section
3, Device
I2C
Configuration)
McBSPs
(internal or external clock source up to 100 Mbps)
1000 Ethernet MAC (EMAC)
Management Data Input/Output (MDIO)
Antenna Interface (AIF)
Frame Synchronization (FSYNC)
64-bit Timers (Configurable)
(internal clock source CPU/6 clock frequency)
SYSCLKOUT
General Purpose Input/Output Port (GPIO)
Decoder Coprocessors
VCP2 (clock source = CPU/3 clock frequency)
TCP2 (clock source = CPU/3 clock frequency)
On-Chip Memory
Size (Bytes)
Organization
CPU Megamodule
Revision ID Register
Revision ID
(MM_REVID. [15:0]) 0x0181 2000)
JTAG Device_ID
JTAG Register (address location: 0x0288 0814)
Frequency
MHz
Cycle Time
ns
Voltage
Core (V)
I/O (V)
PLL1 and PLL1 Controller CLKIN1 Frequency Multiplier
Options
PLL2
DDR Clock
BGA Package
23 X 23 mm
Process Technology
mm
(1) A heatsink and implementation of the SmartReflex solution is required for proper device operation. For more details on SmartReflex, see
Section
7.3.4.
8
Device Overview
Table 2-1. Characteristics of the C6474 Processor
Submit Documentation Feedback
Product Folder Link(s)
6 64-bit or 12 32-bit
32KB L1P Program Cache (SRAM/Cache)
32KB L1D Data Cache (SRAM/Cache)
32KB Data Memory Controller
3072KB Total L2 Unified Memory SRAM/Cache
For details, see
850 - 1200 (850 MHz to 1.2 GHz)
1.18 ns - 0.83 ns (850 MHz to 1.2 GHz CPU)
0.9-V to 1.2-V SmartReflex
Bypass (x1), (x4 to x32)
561-Pin Flip-Chip with BGA CUN/GUN/ZUN
Copyright © 2008–2010, Texas Instruments Incorporated
:TMS320C6474
www.ti.com
C6474
1
1
1
1
2
1
1
1
1
1
16
1
1
3200 KB
64KB L3 ROM
0x0
Section 3.6
(1)
1.1 V
1.8 V, 1.1 V
X10
0.065 mm

Advertisement

Table of Contents
loading

Table of Contents