Texas Instruments TMS320C6474 Manual page 123

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7.8.3.4 PLL Controller Divider 13 Register
The PLL controller divider 13 register (PLLDIV13) is shown in
31
15 14
D13EN
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-14. PLL Controller Divider 13 Register (PLLDIV13) [Hex Address: 029A 0184]
Table 7-28. PLL Controller Divider 13 Register (PLLDIV13) Field Descriptions
Bit Field
31:16 Reserved
15 D13EN
14:5 Reserved
4:0 RATIO
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Reserved
R-0
Value Description
0 Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect.
Divider 13 enable bit.
0 Divider 13 is disabled. No clock output.
1 Divider 13 is enabled.
0 Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect.
0-1Fh Divider ratio bits.
0h-31h ÷1 to ÷32. Divide frequency by 1 to divide frequency by 32.
32h-1Fh Reserved, do not use.
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SPRS552F – OCTOBER 2008 – REVISED JULY 2010
Figure 7-14
Reserved
R-0
5
Peripheral Information and Electrical Specifications
:TMS320C6474
TMS320C6474
and described in Table 7-28.
4
RATIO
R/W-3
16
0
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