Texas Instruments TMS320C6474 Manual page 159

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FSEVT2
FSEVT3
TINPHSEL 0 0 1 2 3
TINPLSEL 0 0 1 2 3
TINPHSEL 1
TINPLSEL 1
TINPHSEL 2
TINPLSEL 2
TINPHSEL 3
TINPLSEL 3
TINPHSEL 4
TINPLSEL 4
TINPHSEL 5
TINPLSEL 5
TOUTSEL 1
TOUTSEL 0
Timer64
0
32
CFG SCR
(SCR F)
vbusp
Note that the TMS320C6474 DSP 64-Bit Timer User's Guide (literature number SPRUG18) uses different
labels for its inputs and outputs. To avoid confusion with respect to numbering, a different convention is
used in this document, as shown in
TIMER SIGNAL NAME
n TINP12
n TINP34
n TOUT12
n TOUT34
7.15.1.1.1 Timer Input Selection Register (TINPSEL)
Timer input selection is handled in the Timer input selection register (TINPSEL). The TINPSEL register is
shown in Figure 7-39
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TIMI0
0 1 2 3
0 1 2 3
0 1 2 3
0 1 2 3
0
Timer64 Timer642
1 2
Figure 7-38. Timer Manager Block Diagram
Table 7-64.
Table 7-64. Timer Pin Naming
RENAMED TO
TINPLn
TINPHn
TOUTLn
TOUTHn
and described in Table
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TIMI1
1 2 3
0 1 2 3
0 1 2 3
0 1 2 3
0 1
Timer64 Timer64
3 4
Timer n input event (low half). Used to drive lower 32-bit timer, 64-bit timer.
Used in watchdog mode.
Timer n input event (high half). Used to drive upper 32-bit timer. Unused in
64-bit or watchdog modes.
Timer n output (low half). Driven by lower 32-bit timer, 64-bit timer, or
watchdog timer as either a pulse or waveform.
Timer n output (high half). Driven by upper 32-bit timer as either a pulse or
waveform. Unused in 64-bit or watchdog modes.
7-65.
Peripheral Information and Electrical Specifications
:TMS320C6474
TMS320C6474
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
SYSCLK/6 TIMO0
2 3
0 1 2 3
0 1 2 3 4 5 6 7 8 91011
0 1 2 3 4 5 6 7 8 91011
Timer Pin Manager
Timer64
5
DESCRIPTION
TIMO1
(TPMGR)
159