Texas Instruments TMS320C6474 Manual page 122

TMS320C6474
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
7.8.3.3 PLL Controller Divider 11 Register
The PLL controller divider 11 register (PLLDIV11) is shown in
31
15 14
D11EN
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-13. PLL Controller Divider 11 Register (PLLDIV11) [Hex Address: 029A 017C]
Table 7-27. PLL Controller Divider 11 Register (PLLDIV11) Field Descriptions
Bit Field
31:16 Reserved
15 D11EN
14:5 Reserved
(1)
4:0 RATIO
(1) For more details, see SYSCLK11 description in
122 Peripheral Information and Electrical Specifications
Reserved
R-0
Value Description
0 Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect.
Divider 11 enable bit.
0 Divider 11 is disabled. No clock output.
1 Divider 11 is enabled.
0 Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect.
0-1Fh Divider ratio bits.
0h-4h Reserved, do not use.
7h-31h ÷8 to ÷ 32. Divide frequency by 8 to divide frequency by 32.
32h-1Fh Reserved, do not use.
Section 7.8.1.1.
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Figure 7-13
Reserved
R-0
5
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and described in Table 7-27.
4
RATIO
R/W-3
16
0