Texas Instruments TMS320C6474 Manual page 133

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7.10.2 DDR2 Memory Controller Peripheral Register Description(s)
The memory map of the DDR2 controller is shown in
HEX ADDRESS
7000 0000
7000 0004
7000 0008
7000 000C
7000 0010
7000 0014
7000 0018
7000 0020
7000 0024 - 7000 004C
7000 0050 - 7000 0078
7000 007C - 7000 00BC
7000 00C0 - 7000 00E0
7000 00E4
7000 00E8 - 7000 00EC
7000 00F0
7000 00F4 - 7000 00FC
7000 0100 - 7FFF FFFF
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Table 7-37. DDR2 Memory Controller Registers
ACRONYM
MIDR DDR2 Memory Controller Module and Revision Register
DMCSTAT DDR2 Memory Controller Status Register
SDCFG DDR2 Memory Controller SDRAM Configuration Register
SDRFC DDR2 Memory Controller SDRAM Refresh Control Register
SDTIM1 DDR2 Memory Controller SDRAM Timing 1 Register
SDTIM2 DDR2 Memory Controller SDRAM Timing 2 Register
- Reserved
BPRIO DDR2 Memory Controller Burst Priority Register
- Reserved
- Reserved
- Reserved
- Reserved
DMCCTL DDR2 Memory Controller Control Register
- Reserved
DDR2IO Control Register
DDR2 ODT control register is at 0x7000 00F0
Bits 1:0 are the ODT status, these bits are Read/Write
00 no termination
01 half termination
11 full termination
Bits 31:2 are Reserved
- Reserved
- Reserved
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SPRS552F – OCTOBER 2008 – REVISED JULY 2010
Table 7-37.
REGISTER NAME
Peripheral Information and Electrical Specifications
:TMS320C6474
TMS320C6474
133