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7.18 Serial RapidIO (SRIO) Port
The SRIO Port on the TCI6487/8 device is a high-performance, low pin-count interconnect aimed for
embedded markets. RapidIO is based on the memory and device addressing concepts of processor buses
where the transaction processing is managed completely by hardware. This enables the RapidIO
interconnect to lower the system cost by providing lower latency, reduced overhead of packet data
processing, and higher system bandwidth, all of which are key for wireless interfaces. The RapidIO
interconnect offers very low pin-count interfaces with scalable system bandwidth based on 10-Gigabit per
second (Gbps) bidirectional links.
The PHY part of the RIO consists of the physical layer and includes the input and output buffers (each
serial link consists of a differential pair), the 8-bit/10-bit encoder/decoder, the PLL clock recovery, and the
parallel-to-serial/serial-to-parallel converters.
The RapidIO interface should be designed to operate at a data rate up to 3.125 Gbps per differential pair.
7.18.1 SRIO Device-Specific Information
The approach to specifying interface timing for the SRIO Port is different than on other interfaces such as
McBSP. For these other interfaces the device timing was specified in terms of data manual specifications
and I/O buffer information specification (IBIS) models.
For the SRIO Port, Texas Instruments (TI) provides a printed circuit board (PCB) solution showing two
DSPs connected via a 1x SRIO link directly to the user. TI has performed the simulation and system
characterization to ensure all SRIO interface timings in this solution are met. The complete SRIO system
solution is documented in the TMS320C6474 DSP SERDES Implementation Guidelines application report
(literature number SPRAAW9).
TI only supports designs that follow the board design guidelines outlined in the
application report.
The Serial RapidIO peripheral is a master peripheral in the TCI6487/8 DSP. It conforms to the RapidIO™
Interconnect Specification, Part VI: Physical Layer 1x/4x LP-Serial Specification, Revision 1.2.
7.18.2 SRIO Register Description(s)
HEX ADDRESS
02D0 0000
02D0 0004
02D0 0008 - 02D0 001C
02D0 0020
02D0 0024 - 02D0 002C
02D0 0030
02D0 0034
02D0 0038
02D0 003C
02D0 0040
02D0 0044
02D0 0048
02D0 004C
02D0 0050
02D0 0054
02D0 0058
02D0 005C
02D0 0060
Copyright © 2008–2010, Texas Instruments Incorporated
Table 7-79. RapidIO Control Registers
ACRONYM
RIOPID
RIO_PCR
-
RIO_PER_SET_CNTL
-
RIO_GBL_EN
RIO_GBL_EN_STAT
RIO_BLK0_EN
RIO_BLK0_EN_STAT
RIO_BLK1_EN
RIO_BLK1_EN_STAT
RIO_BLK2_EN
RIO_BLK2_EN_STAT
RIO_BLK3_EN
RIO_BLK3_EN_STAT
RIO_BLK4_EN
RIO_BLK4_EN_STAT
RIO_BLK5_EN
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Product Folder Link(s)
:TMS320C6474
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
REGISTER NAME
RapidIO Peripheral Identification Register
RapidIO Peripheral Control Register
Reserved
RapidIO Peripheral Settings Control Register
Reserved
RapidIO Peripheral Global Enable Register
RapidIO Peripheral Global Enable Status Register
RapidIO Block0 Enable Register
RapidIO Block0 Enable Status Register
RapidIO Block1 Enable Register
RapidIO Block1 Enable Status Register
RapidIO Block2 Enable Register
RapidIO Block2 Enable Status Register
RapidIO Block3 Enable Register
RapidIO Block3 Enable Status Register
RapidIO Block4 Enable Register
RapidIO Block4 Enable Status Register
RapidIO Block5 Enable Register
Peripheral Information and Electrical Specifications
TMS320C6474
SPRAAW9
171
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