Texas Instruments TMS320C6474 Manual page 145

Multicore digital signal processor
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Table 7-47. Timing Requirements for McBSP as SPI Master: CLKSTP = 10b, CLKXP = 0
(see
Figure
7-30)
NO.
4
t
Setup time, DR valid before CLKX low
su(DRV-CKXL)
5
t
Hold time, DR valid after CLKX low
h(CKXL-DRV)
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
Table 7-48. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
(see
Figure
7-30)
NO.
1
t
Hold time, FSX low after CLKX low
h(CKXL-FXL)
2
t
Delay time, FSX low to CLKX high
d(FXL-CKXH)
3
t
Delay time, CLKX high to DX valid
d(CKXH-DXV)
Disable time, DX high impedance following
6
t
dis(CKXL-DXHZ)
last data bit from CLKX low
Disable time, DX high impedance following
7
t
dis(FXH-DXHZ)
last data bit from FSX high
8
t
Delay time, FSX low to DX valid
d(FXL-DXV)
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) S = Sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
(3) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
(4) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master
clock (CLKX).
CLKX
FSX
DX
Bit 0
DR
Bit 0
Figure 7-30. McBSP Timing as SPI Master: CLKSTP = 10b, CLKXP = 0
Copyright © 2008–2010, Texas Instruments Incorporated
Master: CLKSTP = 10b, CLKXP = 0
PARAMETER
(3)
(4)
1
2
7
8
6
4
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Product Folder Link(s)
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
MASTER
MIN
MAX
12
4
(1)
(2)
MASTER
MIN
MAX
T - 2
T + 3
L - 2
L + 3
-2
4
L - 2
L + 3
3
Bit(n-1)
(n-2)
(n-3)
5
Bit(n-1)
(n-2)
(n-3)
Peripheral Information and Electrical Specifications
:TMS320C6474
TMS320C6474
(1)
SLAVE
UNIT
MIN
MAX
2 - 18P
ns
5 + 36P
ns
SLAVE
UNIT
MIN
MAX
ns
ns
18P + 2.8
30P + 17
ns
ns
6P + 3
18P + 17
ns
12P + 2
24P + 17
ns
(n-4)
(n-4)
145

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