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TMS320C6474
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
5 C64x+ Megamodule
5.1
Megamodule Diagram
The C64x+ Megamodule consists of several components - the C64x+ CPU and associated C64x+
Megamodule core, level-one and level-two memories (L1P, L1D, L2), data trace formatter (DTF),
embedded trace buffer (ETB), the interrupt controller, power-down controller, external memory controller
and a dedicated power/sleep controller (LPSC). The C64x+ Megamodule also provides support for
memory protection and bandwidth management (for resources local to the C64x+ Megamodule).
Figure 5-1
provides a block diagram of the C64x+ Megamodule.
Boot
Controller
PLLC
LPSC
GPSC
58
C64x+ Megamodule
32KB L1P
Memory Controller (PMC) with
Memory Protect/Bandwidth Mgmt
C64x+ DSP Core
Instruction Fetch
16-/32-bit Instruction Dispatch
Control Registers
In-Circuit Emulation
Instruction Decode
Data Path A
A Register File
A31 - A16
A15 - A0
.M1
.L1
.S1
xx
.D1
.D2
xx
Data Memory Controller (DMC) with
Memory Protect/Bandwidth Mgmt
32KB L1D
Figure 5-1. C64x+ Megamodule Block Diagram
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Data Path B
B Register File
B31 - B16
B15 - B0
.M2
xx
.S2
.L2
xx
Copyright © 2008–2010, Texas Instruments Incorporated
:TMS320C6474
www.ti.com
L2 Cache/
SRAM
1024 KB
DMA Switch
Fabric
CFG Switch
Fabric
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