Texas Instruments TMS320C6474 Manual page 152

TMS320C6474
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
Table 7-55. Ethernet MAC (EMAC) Control Registers (continued)
HEX ADDRESS
02C8 026C
02C8 0270
02C8 0274
02C8 0278
02C8 027C
02C8 0280
02C8 0284
02C8 0288
02C8 028C
02C8 0300 - 02C8 03FC
02C8 0400 - 02C8 04FC
02C8 0500
02C8 0504
02C8 0508
02C8 050C - 02C8 05FC
02C8 0600
02C8 0604
02C8 0608
02C8 060C
02C8 0610
02C8 0614
02C8 0618
02C8 061C
02C8 0620
02C8 0624
02C8 0628
02C8 062C
02C8 0630
02C8 0634
02C8 0638
02C8 063C
02C8 0640
02C8 0644
02C8 0648
02C8 064C
02C8 0650
02C8 0654
02C8 0658
02C8 065C
152 Peripheral Information and Electrical Specifications
ACRONYM
FRAME65T127 Transmit and Receive 65 to 127 Octet Frames Register
FRAME128T255 Transmit and Receive 128 to 255 Octet Frames Register
FRAME256T511 Transmit and Receive 256 to 511 Octet Frames Register
FRAME512T1023 Transmit and Receive 512 to 1023 Octet Frames Register
FRAME1024TUP Transmit and Receive 1024 to 1518 Octet Frames Register
NETOCTETS Network Octet Frames Register
RXSOFOVERRUNS Receive FIFO or DMA Start of Frame Overruns Register
RXMOFOVERRUNS Receive FIFO or DMA Middle of Frame Overruns Register
RXDMAOVERRUNS Receive DMA Start of Frame and Middle of Frame Overruns
Register
- Reserved
- Reserved
MACADDRLO MAC Address Low Bytes Register (used in Receive Address
Matching)
MACADDRHI MAC Address High Bytes Register (used in Receive Address
Matching)
MACINDEX MAC Index Register
- Reserved
TX0HDP Transmit Channel 0 DMA Head Descriptor Pointer Register
TX1HDP Transmit Channel 1 DMA Head Descriptor Pointer Register
TX2HDP Transmit Channel 2 DMA Head Descriptor Pointer Register
TX3HDP Transmit Channel 3 DMA Head Descriptor Pointer Register
TX4HDP Transmit Channel 4 DMA Head Descriptor Pointer Register
TX5HDP Transmit Channel 5 DMA Head Descriptor Pointer Register
TX6HDP Transmit Channel 6 DMA Head Descriptor Pointer Register
TX7HDP Transmit Channel 7 DMA Head Descriptor Pointer Register
RX0HDP Receive Channel 0 DMA Head Descriptor Pointer Register
RX1HDP Receive t Channel 1 DMA Head Descriptor Pointer Register
RX2HDP Receive Channel 2 DMA Head Descriptor Pointer Register
RX3HDP Receive t Channel 3 DMA Head Descriptor Pointer Register
RX4HDP Receive Channel 4 DMA Head Descriptor Pointer Register
RX5HDP Receive t Channel 5 DMA Head Descriptor Pointer Register
RX6HDP Receive Channel 6 DMA Head Descriptor Pointer Register
RX7HDP Receive t Channel 7 DMA Head Descriptor Pointer Register
TX0CP Transmit Channel 0 Completion Pointer (Interrupt Acknowledge)
Register
TX1CP Transmit Channel 1 Completion Pointer (Interrupt Acknowledge)
Register
TX2CP Transmit Channel 2 Completion Pointer (Interrupt Acknowledge)
Register
TX3CP Transmit Channel 3 Completion Pointer (Interrupt Acknowledge)
Register
TX4CP Transmit Channel 4 Completion Pointer (Interrupt Acknowledge)
Register
TX5CP Transmit Channel 5 Completion Pointer (Interrupt Acknowledge)
Register
TX6CP Transmit Channel 6 Completion Pointer (Interrupt Acknowledge)
Register
TX7CP Transmit Channel 7 Completion Pointer (Interrupt Acknowledge)
Register
Submit Documentation Feedback
Product Folder Link(s) :TMS320C6474
REGISTER NAME
Copyright © 2008–2010, Texas Instruments Incorporated
www.ti.com