Texas Instruments TMS320C6474 Manual page 170

Multicore digital signal processor
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TMS320C6474
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
EDMA BUS HEX ADDRESS RANGE
5000 0048
5001 0000
5003 0000
5004 0000
5005 0000
5006 0000
5007 0000
5008 0000
5009 0000
500A 0000
500B 0000
N/A
N/A
N/A
N/A
N/A
N/A
N/A
170
Peripheral Information and Electrical Specifications
Table 7-78. TCP2 Registers (continued)
CONFIGURATION BUS HEX
ADDRESS RANGE
-
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
02BA 0000
02BA 004C
02BA 0050
02BA 0060
02BA 0068
02BA 0070
02BA 005C - 02BB FFFF
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ACRONYM
REGISTER NAME
TCPOUT2
TCP2 Output Parameters Register 2
X0
TCP2 Data/Sys and Parity Memory
W0
TCP2 Extrinsic Mem 0
W1
TCP2 Extrinsic Mem 1
I0
TCP2 Interleaver Memory
O0
TCP2 Output/Decision Memory
S0
TCP2 Scratch Pad Memory
T0
TCP2 Beta State Memory
C0
TCP2 CRC Memory
B0
TCP2 Beta Prolog Memory
A0
TCP2 Alpha Prolog Memory
TCPPID
TCP2 Peripheral Identification
Register [Value: 0x0002 1101]
TCPEXE
TCP2 Execute Register
TCPEND
TCP2 Endian Register
TCPERR
TCP2 Error Register
TCPSTAT
TCP2 Status Register
TCPEMU
TCP2 Emulation Register
-
Reserved
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