Boot Sequence - Texas Instruments TMS320C6474 Manual

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HEX ADDRESS RANGE
START
6000 0000 603F FFFF
6040 0000 6FFF FFFF
7000 0000 7000 00FF
7000 0100 7FFF FFFF
8000 0000 9FFF FFFF
A000 0000 AFFF FFFF
B000 0000 BFFF FFFF
C000 0000 CFFF FFFF
D000 0000 DFFF FFFF
E000 0000 EFFF FFFF
F000 0000 FFFF FFFF
2.4

Boot Sequence

The boot sequence is a process by which the DSP's internal memory is loaded with program and data
sections. The DSP's internal registers are programmed with predetermined values. The boot sequence is
started automatically after each power-on reset, warm reset, and system reset. A local reset to an
individual C64x+ Megamodule should not affect the state of the hardware boot controller on the device.
For more details on the initiators of the resets, see
The C6474 device supports several boot processes begins execution at the ROM base address, which
contains the bootloader code necessary to support various device boot modes. The boot processes are
software driven; using the BOOTMODE[3:0] device configuration inputs to determine the software
configuration that must be completed.
2.4.1 Boot Modes Supported
The device supports several boot processes, which leverage the internal boot ROM. Most boot processes
are software driven, using the BOOTMODE[3:0] device configuration inputs to determine the software
configuration that must be completed. From a hardware perspective, there are three possible boot modes:
• No Boot (BOOTMODE[3:0] = 0000b)
With no boot, the CPU executes directly from the internal L2 RAM located at address 0x80 0000.
Note: Device operations are undefined if invalid code is located at address 0x80 0000. This boot mode
is a hardware boot mode.
• Public ROM Boot
The C64x+ Megamodule Core 0 is released from reset and begins executing from the L3 ROM base
address. C64x+ Megamodule Core 0 is responsible for performing the boot process (e.g., from I2C
ROM, Ethernet, or RapidIO), after which C64x+ Megamodule Core 0 brings the other C64x+
megamodule cores out of reset by setting to 1 the EVTPULSE4 bit (bit 4) of the C64x+ Megamodule
Core 0's EVTASRT register. This process is valid only once: writing 1, then writing 1 again will not
bring Core 1 and 2 out of reset again. Then, the C64x+ Megamodule Core 0 begins execution from the
entry address defined in the boot table. The C64x+ Megamodule Core 1 and 2 begin execution from
their L2 RAMs' base address.
The boot process performed by C64x+ Megamodule Core 0 in public ROM boot is determined by the
BOOTMODE[3:0] value in the DEVSTAT register. C64x+ Megamodule Core 0 reads this value, and then
executes the associated boot process in software.
Copyright © 2008–2010, Texas Instruments Incorporated
SIZE
END
4M
252M
256
256M - 256
512M
256M
256m
256m
256m
256m
256m
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Product Folder Link(s)
MEMORY BLOCK DESCRIPTION
C64x+ MEGAMODULE CORE 0 C64x+ MEGAMODULE CORE 1 C64x+ MEGAMODULE CORE 2
DDR2 EMIF Configuration
Section 7.7, Reset Controller.
:TMS320C6474
TMS320C6474
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
Reserved
Reserved
Reserved
DDR2 EMIF Data
AIF Data
Reserved
Reserved
Reserved
Reserved
Reserved
Device Overview 15