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Table 7-7. EDMA3 Transfer Controller 0 Registers (continued)
HEX ADDRESS RANGE
02A2 0300
02A2 0304
02A2 0308
02A2 030C
02A2 0310
02A2 0314
02A2 0318 - 02A2 033C
02A2 0340
02A2 0344
02A2 0348
02A2 034C
02A2 0350
02A2 0354
02A2 0358 - 02A2 037C
02A2 0380
02A2 0384
02A2 0388
02A2 038C
02A2 0390
02A2 0394
02A2 0398 - 02A2 03BC
02A2 03C0
02A2 03C4
02A2 03C8
02A2 03CC
02A2 03D0
02A2 03D4
02A2 03D8 - 02A2 7FFC
HEX ADDRESS RANGE
02A2 8000
02A2 8004
02A2 8008 - 02A2 80FC
02A2 8100
02A2 8104 - 02A2 811C
02A2 8120
02A2 8124
02A2 8128
02A2 812C
02A2 8130
02A2 8134 - 02A2 813C
02A2 8140
02A2 8144 - 02A2 823C
02A2 8240
02A2 8244
02A2 8248
Copyright © 2008–2010, Texas Instruments Incorporated
ACRONYM
REGISTER NAME
DFOPT0
Destination FIFO Options Register 0
DFSRC0
Destination FIFO Source Address Register 0
DFCNT0
Destination FIFO Count Register 0
DFDST0
Destination FIFO Destination Address Register 0
DFBIDX0
Destination FIFO BIDX Register 0
DFMPPRXY0
Destination FIFO Memory Protection Proxy Register 0
-
Reserved
DFOPT1
Destination FIFO Options Register 1
DFSRC1
Destination FIFO Source Address Register 1
DFCNT1
Destination FIFO Count Register 1
DFDST1
Destination FIFO Destination Address Register 1
DFBIDX1
Destination FIFO BIDX Register 1
DFMPPRXY1
Destination FIFO Memory Protection Proxy Register 1
-
Reserved
DFOPT2
Destination FIFO Options Register 2
DFSRC2
Destination FIFO Source Address Register 2
DFCNT2
Destination FIFO Count Register 2
DFDST2
Destination FIFO Destination Address Register 2
DFBIDX2
Destination FIFO BIDX Register 2
DFMPPRXY2
Destination FIFO Memory Protection Proxy Register 2
-
Reserved
DFOPT3
Destination FIFO Options Register 3
DFSRC3
Destination FIFO Source Address Register 3
DFCNT3
Destination FIFO Count Register 3
DFDST3
Destination FIFO Destination Address Register 3
DFBIDX3
Destination FIFO BIDX Register 3
DFMPPRXY3
Destination FIFO Memory Protection Proxy Register 3
-
Reserved
Table 7-8. EDMA3 Transfer Controller 1 Registers
ACRONYM
REGISTER NAME
PID
Peripheral Identification Register
TCCFG
EDMA3TC Configuration Register
-
Reserved
TCSTAT
EDMA3TC Channel Status Register
-
Reserved
ERRSTAT
Error Register
ERREN
Error Enable Register
ERRCLR
Error Clear Register
ERRDET
Error Details Register
ERRCMD
Error Interrupt Command Register
-
Reserved
RDRATE
Read Rate Register
-
Reserved
SAOPT
Source Active Options Register
SASRC
Source Active Source Address Register
SACNT
Source Active Count Register
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Product Folder Link(s)
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
Peripheral Information and Electrical Specifications
:TMS320C6474
TMS320C6474
97
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