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3 Device Configuration
On the C6474 device, certain device configurations (like boot mode, pin multiplexing, and endianness) are
selected at device reset. The status of the peripherals (enabled/disabled) is determined after device reset.
By default, the peripherals on the device are disabled and must be enabled by software before being
used.
3.1
Device Configuration at Device Reset
Table 3-1
describes the C6474 device. The logic level is latched at reset to determine the device
configuration. The logic level can be set by using external pullup/pulldown resistors or by using some
control device to intelligently drive these pins. When using a control device, take care to avoid contention
on the lines when the device is out of reset. The are sampled during power-on reset and are driven after
the reset is removed. To avoid contention, the control device must stop driving the of the DSP.
If a configuration pin must be routed out from the device, the internal pullup/pulldown
(IPU/IPD) resistor should not be relied upon; TI recommends the use of an external
pullup/pulldown resistor.
CONFIGURATION
DEFAULT IPU/IPD
PIN
BOOTMODE[3:0]
LENDIAN
DEVNUM[3:0]
CORECLKSEL
3.2
Peripheral Selection After Device Reset
Several of the peripherals on the C6474 device are controlled by the Power/Sleep Controller (PSC). By
default the AIF, SRIO, TCP, and VCP are held in reset and clock-gated. The memories in these modules
are also in a low-leakage sleep mode. Software will be required to turn these memories on then enable
the modules (turn on clocks and de-assert reset) before these modules can be used.
If one of the above modules is used in the selected boot mode, the ROM code will automatically enable
the used module.
All other modules come up enabled by default and there is no special software sequence to enable.
For more detailed information on the PSC usage, see the TMS320C6474 DSP Power/Sleep Controller
(PSC) User's Guide (literature number SPRUG10).
Copyright © 2008–2010, Texas Instruments Incorporated
Table 3-1. Device Configuration Pins
0000b
Boot Mode Selection
1b
Device Endian Mode
0
Big Endian
1
Little Endian
0000b
Device number
0b
Core Clock Select
0
SYSCLK is shared between the Antenna Interface and the input to PLLCTL1.
1
ALTCORECLK is used as the input to PLLCTL1 and SYSCLK is used only for the
Antenna Interface.
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Product Folder Link(s)
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
NOTE
FUNCTIONAL DESCRIPTION
:TMS320C6474
TMS320C6474
Device Configuration
45
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