Texas Instruments TMS320C6474 Manual page 143

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Table 7-45. Switching Characteristics Over Recommended Operating Conditions for McBSP
(see Figure 7-28)
NO.
1 t Delay time, CLKS high to CLKR/X high for internal CLKR/X
d(CKSH-CKRXH)
generated from CLKS input.
2 t Cycle time, CLKR/X
c(CKRX)
3 t Pulse duration, CLKR/X high or
w(CKRX)
CLKR/X low
4 t Delay time, CLKR high to internal
d(CKRH-FRV)
FSR valid
9 t Delay time, CLKX high to internal
d(CKXH-FXV)
FSX valid
12 t Disable time, DX high impedance
dis(CKXH-DXHZ)
following last data bit from CLKX
high
13 t Delay time, CLKX high to DX valid CLKX ext (DXENA = 0)
d(CKXH-DXV)
Delay time, FSX high to DX valid
14 t ONLY applies when in data delay
d(FXH-DXV)
0 (XDATDLY = 00b)mode
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) Minimum delay times also represent minimum output hold times.
(3) The CLKS signal is shared by both McBSP0 and McBSP1 on this device.
(4) P = 1/CPU clock frequency, in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(5) C = H or L S = sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the
maximum limit (see (4) above).
(6) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
(7) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
Copyright © 2008–2010, Texas Instruments Incorporated
(3)
CLKR/X int
CLKR/X int
CLKR int
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext (DXENA = 1)
FSX int
FSX ext
Peripheral Information and Electrical Specifications
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TMS320C6474
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
MIN MAX
1.4
(4)
10P
(5)
C - 1 C + 1
-2.1
-1.7
1.7
-3.9
2.1
(6)
-3.9 +D1 4 + D2
(6)
2.1
(6)
2.1 + D1 9 + D2
(7)
-2.3 + D1 5.6 + D2
(7)
1.9 + D1 9 + D2
(1) (2)
UNIT
10 ns
ns
(5)
ns
3 ns
3 ns
9
4 ns
9
(6)
ns
(6)
9
(6)
(7)
ns
(7)
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