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TMS320VC5509A Silicon Errata
Advisory I2C_6
Revision(s) Affected:
Details:
Assembler Notification: None
Workaround:
Advisory I2C_8
Revision(s) Affected:
Details:
Assembler Notification: None
Workaround:
Bus Busy Bit Does Not Reflect the State of the I
1.0 and 1.1
The Bus Busy bit (BB) indicates the status of the I
the bus is free and set to '1' when the bus is busy. The I
2
of the I
C bus when it is in reset (IRS bit is set to '0'); therefore, the Bus Busy bit will keep the
state it was at when the peripheral was placed in reset. The Bus Busy bit will stay in that state
2
until the I
C peripheral is taken out of reset (IRS bit set to '1') and a START condition is
2
detected on the I
C bus. When the device is powered up, the Bus Busy bit will stay stuck at
the default value of '0' until the IRS bit is set to '1' and the I
condition.
Systems using a multi-master configuration can be affected by this issue.
Wait a certain period after taking the I
before starting the first data transfer. The period should be set equal to or larger than the total
time it takes for the longest data transfer in the application. By waiting this amount of time, it
can be ensured that any previous transfers finished. After this point, BB will correctly reflect
2
the state of the I
C bus.
1.0 and 1.1
2
When receiving an I
C data stream in master mode (i.e., a read is performed), and the DMA is
started, a DMA synchronization event is triggered upon enabling the DMA channel if a byte is
present in the DRR (even if it has already been read). This leads to the first byte read being a
duplicate of the previous byte that was already read from the DRR.
Set DMA transfers from DRR to read one more byte than necessary and discard the first byte.
2
C bus. The Bus Busy bit is set to '0' when
2
C peripheral cannot detect the state
2
C peripheral out of reset (setting the IRS bit to '1')
DMA Receive Synchronization Pulse Gets Generated Falsely
SPRZ200E
2
2
C Bus When the I
C is in Reset
2
C peripheral detects a START
24
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