User Push Buttons (Active High); User Push Buttons (Active High); Gtx Transceivers And Reference Clocks - Xilinx VC7203 User Manual

Table 1-11: User DIP Switches
Figure 1-9
X-Ref Target - Figure 1-9

User Push Buttons (Active High)

Callout 24,
SW4 and SW5 are active-High user push buttons that are connected to user I/O pins on the
FPGA as shown in
the user.
Table 1-12: User Push Buttons

GTX Transceivers and Reference Clocks

Callout 4,
The VC7203 board provides access to all GTX transceiver and reference clock pins on the
FPGA as shown in
RX-TX lanes. Four lanes are referred to as a Quad.
Note:
VC7203 GTX Transceiver Characterization Board
UG957 (v1.0) October 10, 2012
U1 FPGA Pin Net Name
E42 USER_SW1
C40 USER_SW2
C41 USER_SW3
H40 USER_SW4
H41 USER_SW5
H39 USER_SW6
G39 USER_SW7
G41 USER_SW8
Shows the user test I/O connector J125 (Callout 26,
Figure 1-2.
Table 1-12. These switches can be used for any purpose determined by
U1 FPGA Pin Net Name
P41 USER_PB1
N41 USER_PB2
Figure 1-2.
Figure 1-10. The GTX transceivers are grouped into nine sets of four
QUAD 111 and QUAD 112 do not connect to pins on the XCV485T.
www.xilinx.com
DIP Switch
Reference
Designator
SW2
J125
1 2
USER_SW1
3 4 USER_SW2
5 6 USER_SW3
7 8 USER_SW4
9 10 USER_SW5
11 12
USER_SW6
GND
UG932_C1_09_100712
Figure 1-9: User Test I/O
Reference
Designator
SW5
SW4
Detailed Description
J125 Test Header Pin
2
4
6
8
10
12
Figure 1-2).
21