Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 1099

Offset Name
0xA4 EPAYLOAD
0xA8 Trm
0xAC Nrm
0xAE Mrm
0xB0 TCR
0xB2 ABR_RX_TCTE
0xB4 RxQD_Base_Ext
0xB8 RX_UDC_Base
0xBC TX_UDC_Base
0xC0– —
0xDF
0xE0 TCELL_TMP_BASE_EXT Word
0xE4– —
0xFB
0xFC PAD_TMP_BASE
0xFE —
Freescale Semiconductor
Table 32-13. AAL2 Parameter RAM (continued)
Width
Word Reserved payload. Initialize to 0x6A6A6A6A.
Word (ABR only) The upper bound on the time between F-RM cells for an
active source. TM 4.0 defines the Trm period as 100 msec. The Trm value
is defined by the system clock and the time stamp timer prescaler (See
RTSCR). For time stamp prescalar of 1µs, Trm should be set to 100
ms/1µs = 100,000.
Hword (ABR only) Controls the maximum cells the source may send for each
F-RM cell. Set to 32 cells.
Hword (ABR only) Controls the bandwidth between F-RM, B-RM and user data
cell. Set to 2 cells.
Hword (ABR only) Tag cell rate. The minimum cell rate allowed for all ABR
channels. An ABR channel whose ACR is less than TCR sends only
out-of-rate F-RM cells at TCR. Should be set to 10 cells/sec as defined
in the TM 4.0. Uses the ATMF TM 4.0 floating-point format. Note that the
APC minimum cell rate should be at least TCR.
Hword (ABR only) Points to total of 16 bytes reserved dual-port RAM area used
by the CP. Should be 16-byte aligned. User-defined.
Word Points to the base address of the external RxQD table. The actual
address of the first RxQD in the table is RxQD_Base_Ext + 512*4.
User-defined.
Word Valid only for AAL2 VCs. Points to the base of the RX UDC header table
that contains the UDC headers of the AAL2 VCs. The pointer to a VC
UDC header is: RX_UDC_Base + 16*CH# (where CH# is the ATM
channel number)
Word Valid only for AAL2 VCs. Points to the base of the TX UDC header table
that contains the UDC headers of the AAL2 VCs. The pointer to a VC
UDC header is: TX_UDC_Base + 16*CH# (where CH# is the ATM
channel number)
— Reserved. Should be cleared during initialization.
Transmit Cell Temporary base address. Points to a total of
64*last_AAL2_Ch# octets reserved in external memory for partially filled
cells. Note: TCELL_TMP_BASE_EXT must be on the same bus as the
all the AAL2 data buffers required for CPS, SSSAR and CID switching.
— Reserved. Should be cleared during initialization.
Hword PAD template base address. Points to an internal memory area that
contains the zero cell template. Should be 64-byte aligned. User-defined.
— Reserved. Should be cleared during initialization.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Description
ATM AAL2
32-37