Figure 47. Agp 2.0 Vref Generation And Distribution - Intel 815 Design Manual

AGP/Display Cache Design Guidelines

Figure 47. AGP 2.0 VREF Generation and Distribution

a) 1.5V AGP Card
1.5V AGP
Card
Notes:
1. The resistor dividers should be placed near the GMCH. The AGPREF signal must be 5 mils wide and routed 10 mils from adjacent signals.
2. R7 is the same resistor seen in AGP VDDQ generation example circuit figure (R1)
b) 3.3V AGP Card
3.3V AGP
Card
VDDQ
AGP
Device
GND
The resistor dividers should be placed near the GMCH. The AGPREF signal must be 5 mils wide and routed 25 mils from adjacent signals.
The flexible VREF divider shown in Figure 47 uses a FET switch to switch between the locally
generated VREF (for 3.3V add-in cards) and the source-generated VREF (for 1.5V add-in cards).
Use of the source-generated VREF at the receiver is optional and is a product implementation
issue beyond the scope of this document.
96
+12V
R7
(See note 2)
1 K
TYPEDET#
VrefGC
VDDQ
AGP
REF
Device
GND
VrefCG
+12V
(See note 2)
R7
1 K
TYPEDET#
VrefGC
REF
VrefCG
R9
300 1%
R2
200 1%
U6
REF
C9
mosfet
0.1 uF
R9
300
1%
R2
200
1%
U6
VDDQ
REF
GMCH
C10
mosfet
GND
0.1 uF
®
Intel 815 Chipset Platform Design Guide
VDDQ
C8
500 pF
R5
R6
82
VDDQ
1 K
GMCH
R4
GND
R2
82
1 K
C9
500 pF
VDDQ
C8
500 pF
R5
R6
82
1 K
R2
R4
1 K
82
C9
500 pF
agp_2.0ref_gen_dist
R