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3.9.
PWRGOOD
PWRGOOD is a 3.3 V tolerant input. It is expected
that this signal will be a clean indication that clocks
and the system 3.3 V, 5 V and V
stable and within their specifications. Clean implies
that the signal will remain low, (capable of sinking
leakage current) without glitches, from the time that
the power supplies are turned on until they come
within specification. The signal will then transition
monotonically to a high (3.3 V) state. Figure 11
illustrates the relationship of PWRGOOD to other
system signals. PWRGOOD can be driven inactive
at any time, but power and clocks must again be
3.10.
THERMTRIP#
The Pentium Pro processor protects itself from
catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the
normal operating temperature to ensure that there
are no false trips. The processor will stop all
execution when the junction temperature exceeds
~135°C. This is signaled to the system by the
THERMTRIP# pin. Once activated, the signal
remains latched, and the processor stopped, until
RESET# goes active. There is no hysteresis built into
the thermal sensor itself, so as long as the die
temperature drops below the trip level, a RESET#
pulse will reset the processor and execution will
continue. If the temperature has not dropped beyond
the trip level, the processor will continue to drive
THERMTRIP# and remain stopped.
PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz
P supplies are
CC
Figure 11. PWRGOOD Relationship at Power-On
stable before the rising edge of PWRGOOD. It must
also meet the minimum pulse width specification in
Table 13 and be followed by a 1mS RESET# pulse.
This signal must be supplied to the Pentium Pro
processor as it is used to protect internal circuits
against voltage sequencing issues. Use of this signal
is recommended for added reliability.
This signal does not need to be synchronized for
FRC operation. It should remain high throughout
boundary scan testing.
3.11.
Unused Pins
All RESERVED pins must remain unconnected. All
pins named TESTHI must be pulled up, no higher
than V
P, and may be tied directly to V
CC
named TESTLO must be pulled low and may be tied
directly to V
.
SS
PICCLK must be driven with a clock input, and the
PICD[1:0] lines must each be pulled-up to 3.3 V with
a separate 150Ω resistor, even when the APIC will
not be used.
For reliable operation, always connect unused inputs
to an appropriate signal level. Unused GTL+ inputs
should be pulled-up to V
TT
tolerant inputs should be connected to 3.3 V with a
150Ω resistor and unused active high inputs should
P. All pins
CC
. Unused active low 3.3 V
19
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