System Memory Interface; Table 6-22 Memory Channel A - Intel PENTIUM P6000 - DATASHEET 2010 Datasheet

6.1

System Memory Interface

Table 6-22.Memory Channel A (Sheet 1 of 2)
Signal Name
SA_BS[2:0]
SA_DM[7:0]
SA_DQS[7:0]
SA_DQS#[7:0]
SA_DQ[63:0]
SA_MA[15:0]
SA_CK[1:0]
SA_CK#[1:0]
70
Bank Select: These signals define which
banks are selected within each SDRAM rank.
SA_WE# Write Enable Control Signal: Used with
SA_RAS# and SA_CAS# (along with
SA_CS#) to define the SDRAM Commands.
SA_RAS# RAS Control Signal: Used with SA_CAS#
and SA_WE# (along with SA_CS#) to define
the SRAM Commands.
SA_CAS# CAS Control Signal: Used with SA_RAS#
and SA_WE# (along with SA_CS#) to define
the SRAM Commands.
Data Mask: These signals are used to mask
individual bytes of data in the case of a
partial write and to interrupt burst writes.
When activated during writes, the
corresponding data groups in the SDRAM are
masked. There is one SA_DM[7:0] for every
data byte lane.
Data Strobes: SA_DQS[7:0] and its
complement signal group make up a
differential strobe pair. The data is captured
at the crossing point of SA_DQS[7:0] and its
SA_DQS#[7:0] during read and write
transactions
Data Strobe Complements: These are the
complementary strobe signals.
Data Bus: Channel A data signal interface to
the SDRAM data bus.
Memory Address: These signals are used to
provide the multiplexed row and column
address to the SDRAM.
SDRAM Differential Clock: Channel A
SDRAM Differential clock signal pair. The
crossing of the positive edge of SA_CK and
the negative edge of its complement
SA_CK# are used to sample the command
and control signals on the SDRAM.
SDRAM Inverted Differential Clock:
Channel A SDRAM Differential clock signal-
pair complement.
Description
Signal Description
Direction/Buffer
Type
O
DDR3
O
DDR3
O
DDR3
O
DDR3
O
DDR3
I/O
DDR3
I/O
DDR3
I/O
DDR3
O
DDR3
O
DDR3
O
DDR3
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