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6. SGMII Ethernet Connections
This section describes the MachXO5T-NX Development Board SGMII application for Ethernet connections. This board
can support two independent Ethernet connections through on-board SGMII PHY devices PHY0 and PHY1, which is
GPY115C0VI from Maxlinear, as shown in
PHY devices.
LFMXO5-100T
(U3)
Table 6.1. SGMII Ethernet PHY Interfacing
PHY Interface
PHY0 (U6)
PHY1 (U7)
The pin strapping configuration for both SGMII PHY devices have been implemented on board, as shown in
and
Table
6.3.
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02058-1.0
Figure
6.1.
Table 6.1
Management Port 0
SGMII TX0
SGMII RX0
SGMII TX1
SGMII RX1
Management Port 1
Figure 6.1. SGMII ×2 Interfacing
LFMXO5-100T Ball
Location
P6
U2
R4
T5
P2
R2
T1
U1
P7
T2
P4
U5
R5
P5
P1
R1
MachXO5T-NX-Development Board
listed the signals from the FPGA interfacing with SGMII
PHY0
TPI0
(U6)
PHY1
TPI1
(U7)
Net Name
PHY0_MDIO
PHY0_MDC
PHY0_MDINT
PHY0_EXINT0
SGMII_FPGA_RX0P
SGMII_FPGA_RX0N
SGMII_FPGA_TX0P
SGMII_FPGA_TX0N
PHY1_MDIO
PHY1_MDC
PHY1_MDINT
PHY1_EXINT0
SGMII_FPGA_RX1P
SGMII_FPGA_RX1N
SGMII_FPGA_TX1P
SGMII_FPGA_TX1N
Evaluation Board User Guide
Port A
RJ45 x2
(J14)
Port B
Pin Number of PHY Device
10
11
12
13
25
24
27
28
10
11
12
13
25
24
27
28
Table 6.2
19
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