C Download Interface; Figure 3.5. I 2 C Programming Mode; Table 3.1. Config Jtag Connections; Table 3.2. Other Config Jtag Control Signals - Lattice Semiconductor MachXO5T-NX-Development Board User Manual

MachXO5T-NX-Development Board
Evaluation Board User Guide

Table 3.1. Config JTAG Connections

J1 Pin Number
1
2
3
4
5
6
7
8
The MachXO5T-NX Development Board also provides test points for other dedicated JTAG configuration pins as shown
in Table 3.2.

Table 3.2. Other Config JTAG Control Signals

Net Name
JTAGEN
PROGRAMN
INITN
DONE
JP2 for JTAGEN is used to pull down the JTAGEN to disable JTAG port. Using SW5 push button with PROGRAMN reloads
the bitstream from internal Flash when PROGRAMN_PORT function is enabled by software.
2
3.2. I

C Download Interface

The USB hub on the PC can also detect the addition of the USB function on Config FTDI Port B. You can select the port
FTUSB-1 on the programmer interface for the accessing from Config FTDI Port B to the LFMXO5-100T dedicated I
download port (Figure 3.2) that is named as FTDI_SDA/FTDI_SCL with 2.2 kΩ pull up resistor each. The Diode D21 is
2
inserted to support I C clock stretching mode with JP27 added to drive FTDI_SCL from FTDI, but JP27 cannot be added
2
when using I C config mode.
Table 3.3 summarizes the interconnection with LFMXO5-100T and its supported circuits. JP12 and JP13 are used to
2
connect the dedicated I C download port of LFMXO5-100T with the bridge I
2
case you need access I C download port from other on board headers other than Config FTDI part. For the detail
connection from other headers to bridge I
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14
JTAG Net Name
VCCIO2
NX_TDO
NX_TDI
—
—
NX_TMS
GND
NX_TCK
LFMXO5-100T Ball Location
A14
G10
H10
H11
Figure 3.5 details the design of Config FTDI Port B for dedicated I
2
C bus SDA0/SCL0, refer to the
2
Figure 3.5. I C Programming Mode
LFMXO5-100T Ball Location
for JTAG
—
E16
C16
—
—
B16
—
B19
LED Indicator
—
—
D11
D10
2
C bus SDA0/SCL0 cross the whole board, in
User I2C Interface
Optional SSPI Function
—
SSI
SSO
—
—
SCSN
—
SCLK
Test Point
Pin 2 of JP2
—
TP5
TP6
2
C
2
C download interface.
section.
FPGA-EB-02058-1.0