Optional Sma Headers; Figure 8.1. Sma Interfacing For X1 Serdes Rx And Tx; Figure 8.2. Sma Interfacing For X1 Serdes Rx And Tx; Table 8.1. Connections For Sma Serdes Signal Pair - Lattice Semiconductor MachXO5T-NX-Development Board User Manual

MachXO5T-NX-Development Board
Evaluation Board User Guide

8. Optional SMA Headers

MachXO5T-NX Development Board provides two pairs of high speed SMA footprints to support flexible Serdes Protocol
validation, with x1 RX and TX signal pairs, as shown in
SF2921-61345-2S from Amphenol. The signal mapping was shown as

Table 8.1. Connections for SMA Serdes signal pair

Reference
SMA0
SMA1
SMA2
SMA3
Note: LFMXO5-100T engineering samples cannot support additional PCIe lane via the SMA.
MachXO5T-NX Development Board also provides a pair of high-speed SMA footprints to support SerDes extension
reference clock input as shown in
and the LVDS clock is recommended to be connected. The signal mapping is shown in

Table 8.2. Connections for External SMA Reference Clock

SMA
SMA4
SMA5
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Figure 8.1. Their SMA footprint is compatible with

Figure 8.1. SMA Interfacing for x1 Serdes RX and TX

Net Name
SD3_RXp
SD3_RXn
SD3_TXp
SD3_TXn
Figure 8.2. Their SMA footprint is compatible with SF2921-61356-2S from Amphenol

Figure 8.2. SMA Interfacing for x1 SerDes Rx and Tx

Net Name
EXT1_CLKp
EXT1_CLKn
Table 8.1.
LFMXO5-100T Ball Location
Table 8.2.
LFMXO5-100T Ball Location
B13
C13
A8
A9
A11
A12
FPGA-EB-02058-1.0