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MachXO5T-NX-Development Board
Evaluation Board User Guide
1.3. LFMXO5-100T Device
The MachXO5T-NX Development Board features the LFMXO5-100T device in a 400-ball caBGA package. This device
offers a variety of features and programmability that enhances Secure Control PLD functionality with Multiple Boot
capabilities. Its cryptographic engine supports user-mode security features. Along with the cryptographic engine,
numerous system functions are included such as four PLLs and 3,744 kbits of embedded RAM plus hardened
2
implementations of I
C and SPI, MachXO5T-NX FPGAs feature one hard PCIe link layer IP block which supports PCIe
Gen1, Gen2 with one or two ×1 configuration, with flexible, high performance I/O support numerous single-ended and
differential standards including LPDDR4 controller and SLVS. For more information on the capabilities of LFMXO5-100T
device, see
MachXO5-NX Family Data Sheet
(FPGA-DS-02102).
© 2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02058-1.0
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