Table 12.2. Versa J9 Header Pin Connections - Lattice Semiconductor MachXO5T-NX-Development Board User Manual

Notes:
*
Net is optionally connected to power source through resistor DNI.
**
Net is optionally connected to power source through resistor DI.

Table 12.2. Versa J9 Header Pin Connections

J9 Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Notes:
*
Net is optionally connected to power source through resistor DNI.
**
Net is optionally connected to power source through resistor DI.
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FPGA-EB-02058-1.0
Net Name
HPE_RESOUT#
GND
EXPCON_IO0
EXPCON_IO1
EXPCON_IO2
EXPCON_IO3
EXPCON_IO4
EXPCON_IO5
EXPCON_IO6
EXPCON_IO7
EXPCON_IO8
EXPCON_IO9
EXPCON_IO10
EXPCON_IO11
EXPCON_IO12
EXPCON_IO13
EXPCON_IO14
EXPCON_IO15
GND
EXPCON_3V3**
EXPCON_IO16
GND
EXPCON_IO17
GND
EXPCON_IO18
GND
EXPCON_IO19
EXPCON_IO20
EXPCON_IO21
GND
EXPCON_IO22
EXPCON_IO23
EXPCON_IO24
GND
EXPCON_IO25
EXPCON_IO26
EXPCON_IO27
CARDSEL#*
EXPCON_IO28
GND
MachXO5T-NX-Development Board
Evaluation Board User Guide
LFMXO5-100T Ball Location
H14
—
H15
H13
F15
H16
D16
F16
C17
A16
B18
B17
F17
E17
E18
B20
F18
G16
—
—
G17
—
C19
—
C20
—
D20
D19
E19
—
F19
E20
F20
—
G20
G19
H17
—
H18
—
33